The Two-Cycle AHB ERROR

Where the interviewer goes next. Open a node to practise that follow-up.

What IfProve ItBreak ItCompare

1. The Two-Cycle AHB ERROR
2. What IfCancelling After an ERRORL2 Mid-Level

   Beat 2 of an INCR4 write gets ERROR, and the manager drives IDLE in the second error cycle. What happens to beat 3, and must the manager redo the burst later?

   Data phase         beat 1   beat 2   beat 2
   HRESP              OKAY     ERROR    ERROR
   HREADY             1        0        1
   Address HTRANS     SEQ      SEQ      IDLE
   What happens to the pipelined beat 3?

   Reveal the Model Answer

   Beat 3's address phase was on the bus during the first error cycle. The manager turns it into IDLE in the second cycle. So no subordinate ever takes it, because it is never accepted as NONSEQ or SEQ with HREADY high. The manager need not rebuild the remaining beats later. During that waited cycle, it may also change the address, which the normal hold rule forbids.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Beat 3's address phase was on the bus during the first error cycle. Key point 2 The manager turns it into IDLE in the second cycle. Key point 3 So no subordinate ever takes it, because it is never accepted as NONSEQ or SEQ with HREADY high. Key point 4 The manager need not rebuild the remaining beats later. Key point 5 During that waited cycle, it may also change the address, which the normal hold rule forbids.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer explains that the cancelled beat is never accepted by any subordinate. It also says the manager need not resend the rest of the burst.

   • Lesson P4.5The Two-Cycle ERROR
   • Lesson P4.11An AHB Agent: The Pipelined Driver and Monitor
   • Problem P4.5.1A One-Cycle Error
3. What IfA Manager That Continues After ERRORL2 Mid-Level

   What if the manager does not cancel, and drives beats 3 and 4 after the ERROR? Is that legal, and what should your checker accept?

   Reveal the Model Answer

   It is legal: cancelling the rest of the burst is allowed, not required. So the checker must accept both IDLE in the second error cycle and a burst that carries on. The subordinate answers the later beats normally. A checker that flags the continued burst reports a false failure on a legal manager.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 It is legal: cancelling the rest of the burst is allowed, not required. Key point 2 So the checker must accept both IDLE in the second error cycle and a burst that carries on. Key point 3 The subordinate answers the later beats normally. Key point 4 A checker that flags the continued burst reports a false failure on a legal manager.

   Spec Misquote

   "After an ERROR the manager must abandon the burst."

   The spec allows either choice. A checker built on that belief fails legal managers.

   Source AMBA AHB Protocol Specification IHI 0033C §3.6.2 Early burst termination

   Missed Corner

   "An ERROR on a read stops the manager using the data."

   The manager may still use it. That is why the spec recommends driving HRDATA to zero on an errored read.

   Source AMBA AHB Protocol Specification IHI 0033C §5.1.3 ERROR response

   • Lesson P4.5The Two-Cycle ERROR
   • Problem P4.5.1A One-Cycle Error
4. Break ItAsserting the Two-Cycle ERRORL2 Mid-Level

   A subordinate sometimes gives a one-cycle ERROR. Write assertions that catch it.

   Reveal the Model Answer

   Check both directions. A first ERROR cycle (HRESP high, HREADYOUT low) must be followed by a second (HRESP high, HREADYOUT high). And a second cycle must be preceded by a first. The one-cycle error passes the first property vacuously: there is no first cycle to trigger it. It fails only the second, so a checker with just one of them misses it.

   ap is 1 while a NONSEQ sits in the address phase. A token on the address wire is an address phase accepted at that edge.

   1. Cycle 1

      The write to 0x8000 is accepted at this edge: its data phase is the next cycle.

   2. Cycle 2

      The memory ends that data phase with HRESP and HREADY high together. The property err_first fails here: an ERROR must start with HREADY low. The same edge accepts the next address phase, the write to 0x600.

   3. Cycle 3

      The write to 0x600 completes with 77. A two-cycle ERROR would have given the manager the edge before this one to drive IDLE instead.

   Measured on the lesson bench. This ERROR has one cycle only, so the next write is accepted and completes.

   RUNVerilator · simulator service

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: t=65 second_needs_first failed t=90 done

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Check both directions. Key point 2 A first ERROR cycle (HRESP high, HREADYOUT low) must be followed by a second (HRESP high, HREADYOUT high). Key point 3 And a second cycle must be preceded by a first. Key point 4 The one-cycle error passes the first property vacuously: there is no first cycle to trigger it. Key point 5 It fails only the second, so a checker with just one of them misses it.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer writes both implications, first cycle to second and second cycle back to first. It explains why one of them alone misses the one-cycle error.

   • Lesson P4.10The AHB Checker
   • Lesson P4.5The Two-Cycle ERROR
   • Problem P4.10.1Properties for the AHB Link
5. CompareError Responses Across AMBAL2 Mid-LevelL3 Senior

   Compare AHB ERROR with APB PSLVERR and AXI SLVERR and DECERR. Where does an AHB decode error come from?

   Reveal the Model Answer

   AHB has one response bit, so a decode error is ERROR from the default subordinate for unmapped NONSEQ or SEQ transfers. APB's PSLVERR counts only in the single completion cycle, and needs no second cycle because APB is not pipelined. AXI separates SLVERR (the end point refused) from DECERR (no end point). It reports per read beat and once per write, and never shortens a burst. Bridges map PSLVERR to HRESP or to RRESP/BRESP.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 AHB has one response bit, so a decode error is ERROR from the default subordinate for unmapped NONSEQ or SEQ transfers. Key point 2 APB's PSLVERR counts only in the single completion cycle, and needs no second cycle because APB is not pipelined. Key point 3 AXI separates SLVERR (the end point refused) from DECERR (no end point). Key point 4 It reports per read beat and once per write, and never shortens a burst. Key point 5 Bridges map PSLVERR to HRESP or to RRESP/BRESP.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer gets the error signalling of AHB, APB and AXI right. It knows the default subordinate makes the decode error on AHB.

   • Lesson P4.5The Two-Cycle ERROR
   • Lesson P4.8Decoder, Multiplexor and the Default Subordinate
   • Lesson P3.4Errors: PSLVERR
   • Lesson P2.13Responses and Exclusive Access
   • Problem P4.8.2Decoder and Default Subordinate
6. Prove ItSolve P4.5.1: A One-Cycle ErrorSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem P4.5.1