ASIC Point Explore

← Protocols Interviews

Interview Question · Waveform

The APB Setup and Access Phases

L0 FresherL1 Juniorapbtransferstate machine
  • Asked at NVIDIA
  • Likely at Broadcom
  • Likely at Intel

The interviewer asks

Draw an APB write with no wait states, then one with a wait state. What happens in each cycle, and what is the shortest an APB transfer can be?

Reveal the Model Answer

Every APB transfer starts with one SETUP cycle. In it PSEL is high, PENABLE is low, and the address, direction and write data are valid. One or more ACCESS cycles follow, with PENABLE high. The transfer completes at the edge where PSEL, PENABLE and PREADY are all high. So the minimum is two cycles, and each cycle of PREADY low adds one. Afterwards the bus returns to IDLE, or goes straight to SETUP for the next transfer, with PENABLE low again.

A write with one wait state
01234PSELPENABLEPREADYPADDRx10xPWDATAx5ax

Cycle 1 is SETUP, cycles 2 and 3 are ACCESS. The write lands at the end of cycle 3, the only cycle with PSEL, PENABLE and PREADY all high. PREADY is a don't-care while PENABLE is low.

  1. IDLE

    PSEL low. The default state.

  2. SETUP

    PSEL high, PENABLE low, for exactly one cycle. Address, direction and write data are valid.

  3. ACCESS

    PENABLE high. Stays here while PREADY is low; everything set in SETUP is held.

  4. Exit

    PREADY high ends the transfer. The bus goes back to IDLE, or straight to SETUP if another transfer follows. PSEL may stay high for the same completer.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Fresher)

A good fresher answer names the SETUP and ACCESS phases and says a transfer takes at least two cycles. It ends when PSEL, PENABLE and PREADY are all high.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompareScale It

  1. The APB Setup and Access Phases
  2. WhyWhy APB Has a Setup CycleL1 Junior

    Why does APB spend a whole cycle on SETUP? Why not finish a register access in one cycle?

    Reveal the Model Answer

    SETUP gives the completer a full cycle with a stable address and select. Then PENABLE marks the cycle that counts. The completer can decode in SETUP and act on a single edge with very little logic. APB trades speed for that simplicity. It is not pipelined and every transfer costs at least two cycles, which is fine for occasional register traffic.

    The Operating States of APBA write followed by a read, walked through the three states.
    The operating states of APBA write followed by a read, walked through the three states. state IDLE PSEL = 0 state SETUP PSEL = 1, PENABLE= 0, one cycle state ACCESS PSEL = 1, PENABLE= 1, until PREADY completer Completer holds PREADY low towait transfernext edgePREADY = 1, anothertransferPREADY = 1, notransferPREADY
    1. Request

      The bridge has a write. It drives the address, the direction and the data, and raises PSEL: SETUP.

      Follow the calls, values and waits
      1. data transfer: IDLE → SETUP
    2. Enable

      One edge later PENABLE rises: ACCESS. The address, data and controls do not change.

      Follow the calls, values and waits
      1. data transfer: SETUP → ACCESS
    3. Wait

      The completer holds PREADY at 0 for as long as it needs. The bus stays in ACCESS and nothing changes.

    4. Next transfer

      PREADY is 1, the write completes, and a read is waiting. PENABLE drops, PSEL stays: SETUP again, with no idle cycle.

      Follow the calls, values and waits
      1. data transfer: ACCESS → SETUP
    5. Done

      The read completes with nothing behind it: PSEL falls and the bus is IDLE.

      Follow the calls, values and waits
      1. data transfer: ACCESS → IDLE
    Read the diagram as text
    • IDLE: PSEL = 0
    • SETUP: PSEL = 1, PENABLE = 0, one cycle
    • ACCESS: PSEL = 1, PENABLE = 1, until PREADY
    • Completer: holds PREADY low to wait
    • IDLE → SETUP: transfer
    • SETUP → ACCESS: next edge
    • ACCESS → SETUP: PREADY = 1, another transfer
    • ACCESS → IDLE: PREADY = 1, no transfer
    • Completer → ACCESS: PREADY

    The requester moves the bus between states; the completer can only keep it in ACCESS.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer links the SETUP cycle to decode time and to a completer that acts on one edge. It accepts the two-cycle cost as the price of a cheap interface.

  3. What IfWhat Holds During APB Wait StatesL1 JuniorL2 Mid-Level

    The completer holds PREADY low for three cycles. What is the requester allowed to change during those cycles?

    Reveal the Model Answer

    Nothing it set in SETUP: PADDR, PWRITE, PSEL, PENABLE and PPROT stay unchanged. So do PWDATA and PSTRB for a write, and any user request signals. The hold lasts from the SETUP-to-ACCESS transition until PREADY is high. The only free signal in that window is the completer's own PREADY. Any number of wait states is legal, from zero upwards.

    The Address That Moved in a Wait StateA write to 0x1c with two wait states; PADDR moves to 0x20 in the second one. Then two reads.
    PSELPENABLEPADDRPREADYRequestermoves PADDR in a waitCompleter p0acts at the completion edge

    A token flies at each completion edge: the write data to the completer, the read data back.

    01234567clkpselpenablepwritepaddr1c201c20pwdata660preadyprdata066
    1. Cycle 0

      Setup of the write: PSEL high, PENABLE low, PADDR = 0x1c, PWDATA = 0x66. From here to the completion edge every one of these must stay put.

    2. Cycle 2

      The second access cycle, still waiting: PADDR is now 0x20. The property stable_ctl fails at this edge, and the procedural checker prints stable at the same edge.

    3. Cycle 3

      PREADY is 1: the completion edge. The completer acts on what it sees now, so 0x66 lands at 0x20.

    4. Cycle 5

      The read of 0x1c returns 0x00. The data was never written there.

    5. Cycle 7

      The read of 0x20 returns 0x66: the neighbour took the write.

    Measured on the lesson bench. PADDR moved during a wait state, so the write of 0x66 landed at 0x20, not 0x1c.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer lists the signals that must hold. It says the hold starts when SETUP moves to ACCESS, not at the first wait cycle.

  4. Break ItA Completer That Never AnswersL2 Mid-LevelL3 Senior

    A completer holds PREADY low forever. Is that an APB protocol violation? How does your bench catch it?

    Reveal the Model Answer

    It is not a protocol violation, because APB allows any number of wait states. "Too long" is a system property, so a protocol checker cannot call it wrong. The bench uses a watchdog instead, with a limit taken from the peripheral's documented maximum. The watchdog reports a hang when the wait reaches that limit. In formal, the same requirement is a bounded response property, or a liveness property with fairness assumptions on the completer's inputs.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer says the APB spec allows waits of any length. It puts the time limit in a separate watchdog, not in the protocol checker.

  5. Scale ItTimeouts in an APB BridgeL3 SeniorL4 Staff

    A completer hangs with PREADY low. Should the bridge time out? What does it return, and what is the risk?

    Reveal the Model Answer

    A timeout is system policy, not protocol. After a programmed limit, the bridge returns SLVERR so the CPU is not stuck forever. The risk is on the APB side: the requester must hold the transfer until PREADY, so the bridge cannot legally abandon it. It either keeps that segment blocked and fails every later access, or resets the completer. Specify which, raise an interrupt, and verify that recovery path.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Senior)

    A good senior answer separates the AXI response from the stuck APB transfer. It knows the bridge cannot simply drop an APB access that has started.

  6. Break ItWhat an APB Checker Cannot SeeL2 Mid-LevelL3 Senior

    Your APB protocol checker passes on every test. Which completer bugs can still be in the design?

    Reveal the Model Answer

    Every bug that keeps the wires legal can remain, because a wire checker only proves the protocol. A completer that acts in every selected cycle still obeys the handshake. So does one that returns read data one transfer late, ignores PSTRB, acts without its PSEL, or raises PSLVERR a cycle early. A register model or scoreboard that predicts data and responses catches the rest. But it needs traffic with wait states, back-to-back transfers, sparse strobes and errors.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer separates checking the rules on the wires from checking the data. It names at least three bugs that keep the wires legal.

    Missed Corner

    If the APB property module and the register read-back both pass, the completer is correct.

    A full-word write to RAM with zero wait states makes faulty completers look the same as a good one. Without wait states, partial strobes and error cases, the scoreboard never sees the difference.

    Source Lesson P3.10 and problem P3.10.2 (six faulty completers behave like the correct block under full-word zero-wait writes)

  7. Prove ItSolve P3.10.2: Break the CompletersSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P3.10.2

  8. CompareWhy Registers Live on APBL0 FresherL1 Junior

    Your SoC already has an AXI interconnect. Why put the UART, timer and GPIO registers behind an APB bridge, instead of giving each one an AXI port?

    Reveal the Model Answer

    Register traffic is rare, small and tolerant of latency, so APB's simplicity wins. It runs one transfer at a time, with no bursts and no IDs. Each peripheral needs only a tiny state machine, and there are few wires to route. One bridge pays the AXI cost once for many peripherals. The price is throughput: at least two cycles per transfer, and one slow completer stalls the whole APB segment. So blocks that move real data stay on AXI or AHB.

    One Register Write, from the Processor to a PeripheralThe processor writes a timer register. The request crosses the system bus, the bridge turns it into an APB transfer and selects the timer.
    One register write, from the processor to a peripheralThe processor writes a timer register. The request crosses the system bus, the bridge turns it into an APB transfer and selects the timer. manager Processor issues a store to thetimer bus Interconnect AXI or AHB bridge APB bridge the one requester completer UART PSEL0 completer Timer PSEL1 completer GPIO PSEL2 writeAPB regionPSEL0PSEL1PSEL2
    1. System bus

      The store leaves the processor as a write on the system bus.

      Follow the calls, values and waits
      1. data store: Processor → Interconnect
    2. To the bridge

      The interconnect decodes the address into the APB region and passes the write to the bridge.

      Follow the calls, values and waits
      1. data store: Interconnect → APB bridge
    3. One select

      The bridge decodes the address again, raises PSEL1 only, and runs one APB transfer. The UART and the GPIO see the same wires and ignore them.

      Follow the calls, values and waits
      1. data store: APB bridge → Timer
    Read the diagram as text
    • Processor: issues a store to the timer
    • Interconnect: AXI or AHB
    • APB bridge: the one requester
    • UART: PSEL0
    • Timer: PSEL1
    • GPIO: PSEL2
    • Processor → Interconnect: write
    • Interconnect → APB bridge: APB region
    • APB bridge → UART: PSEL0
    • APB bridge → Timer: PSEL1
    • APB bridge → GPIO: PSEL2

    The bridge turns one system-bus write into one APB transfer. Only the timer's select goes high.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Fresher)

    A good fresher answer says APB is cheap, low-power and simple. It is meant for peripheral registers and connects to the main bus through a bridge.

    Misconception

    APB is chosen because it has lower latency than AXI.

    APB is chosen for low cost and low complexity. Every transfer takes at least two cycles, and nothing overlaps. A register access through a bridge is slower, not faster.

    Source AMBA APB Protocol Specification IHI 0024E §1.1 About the APB protocol

    Half-Truth

    APB is just AXI4-Lite with a different name.

    AXI4-Lite keeps independent read and write channels, each with its own valid/ready handshake. APB shares one address and control path. Its read and write data cannot move at the same time.

  9. CompareFrom APB2 to APB5L1 Junior

    What did APB3, APB4 and APB5 each add?

    Reveal the Model Answer

    APB3 added wait states and errors, through PREADY and PSLVERR. APB4 added protection and sparse writes, through PPROT and PSTRB. APB5 added wake-up signalling, user signals and parity protection. The current issue also adds Realm Management Extension support as an option. An APB2 completer has neither PREADY nor PSLVERR, so a bridge ties them off for it.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer places PREADY and PSLVERR in APB3, and PPROT and PSTRB in APB4.

  10. What IfOne Slow Peripheral on the APB SegmentL2 Mid-LevelL3 Senior

    One peripheral on your APB segment takes 50 wait states for some registers. What happens to the other peripherals, and what would you do about it?

    Reveal the Model Answer

    Every access behind that bridge waits, because APB carries one transfer at a time and nothing starts until the waiting one completes. One fix is to give the slow peripheral its own APB segment or bridge. Another is to make it answer at once with a busy bit that software polls. A third is posted writes: the bridge answers before APB finishes, so it loses PSLVERR for those writes. Pick by the latency budget of the time-critical peripherals.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer explains that one slow transfer blocks everything behind it, because APB carries one transfer at a time.

  11. Scale ItDesigning an AXI-to-APB BridgeL3 SeniorL4 Staff

    Design an AXI4-to-APB bridge. What must it do, which decisions are yours, and how would you verify it?

    Reveal the Model Answer

    The bridge is the AXI subordinate and the APB requester. It decodes PSELx and makes one APB transfer per AXI beat. Each transfer uses the aligned address, with WSTRB on PSTRB and AxPROT on PPROT. It maps PSLVERR to SLVERR: per beat in RRESP, and merged into the single BRESP. Your decisions are read/write arbitration, DECERR for unmapped addresses, a timeout policy and posted writes. Verify it with checkers on both sides and an end-to-end scoreboard.

    A 2-beat AXI Write Through the BridgeMeasured on the bench: cycle 0 is edge 3, where AW is taken; B is sent at edge 10.
    AWWBPSELPWDATAPREADYAXI manageraxi_write, 2 beatsBridgeone beat at a timeAPB completerRAM at 0x000

    Pills: an AXI beat taken by the bridge, then the same data written on APB.

    01234567clkawvalidwvalidwreadypselpenablepreadypwdata01111111122222222bvalid
    1. Cycle 0

      AW is taken: a 2-beat write of words at 0x10.

    2. Cycle 1

      Beat 0 is taken from W. The bridge has room for one beat only.

    3. Cycle 2

      APB setup for 0x10 with 11111111. Beat 1 is already offered on W and must wait: wready is 0.

    4. Cycle 3

      APB access with pready 1: the first word is written.

    5. Cycle 4

      Now the bridge takes beat 1.

    6. Cycle 5

      Setup for 0x14 with 22222222.

    7. Cycle 6

      The second word is written. That was the last beat.

    8. Cycle 7

      B is sent with OKAY: one response for the whole AXI write.

    Three edges per beat here: take the W beat, APB setup, APB access. The AXI side could have moved a beat on every edge.

    AXI sideAPB sideNote
    One burst of N beatsN transfers, each SETUP + ACCESSAPB has no burst signals; the bridge computes each beat's address
    Beat address (maybe unaligned)Aligned PADDRAn unaligned PADDR is UNPREDICTABLE; the strobes pick the bytes
    WSTRB of the beatPSTRBAll PSTRB low on reads
    AxPROTPPROTSame three bit meanings: privileged, non-secure, instruction
    RRESP per beat, one BRESPPSLVERR per transferMerging writes is a bridge decision
    Address with no completerNo transferAnswer DECERR

    What the bridge translates. The table is ours; each row is sourced in review.claims.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Senior)

    A good senior answer covers one APB transfer per beat, aligned PADDR with strobes, PPROT, the response mapping and merge, and DECERR. It keeps the AXI rules: every read beat comes back, and one BRESP follows the last W beat.

    Misconception

    Pass the burst start address to APB and let the peripheral increment it.

    APB has no length or burst signal, so every transfer stands alone. The bridge must compute each beat's address from the AXI burst rules. It then issues one APB transfer per beat.

    Source AMBA APB Protocol Specification IHI 0024E §2.1 AMBA APB signals (Table 2-1 has no burst or length signal); lesson P3.7 (a 4-beat burst becomes four APB transfers)

    Spec Misquote

    On PSLVERR in the middle of a read burst, stop and return the error at once.

    AXI requires every read data transfer of the burst to be returned, whatever the response. A write gets exactly one completion response. Stopping early breaks the AXI side.

    Source AMBA AXI Protocol Specification IHI 0022L §A3.3.2 Read response; §A3.3.1 Write response

    Missed Corner

    Send the unaligned AXI byte address straight to PADDR.

    An unaligned PADDR is permitted, but its result is UNPREDICTABLE: the completer may use it, align it or error. Send the aligned word address, and select the bytes with PSTRB.

    Source AMBA APB Protocol Specification IHI 0024E §2.1.1 Address bus

  12. WhyUnmapped Addresses Behind an APB BridgeL2 Mid-LevelL3 Senior

    What should the bridge answer for an address that no APB completer owns? Why not just start the APB transfer anyway?

    Reveal the Model Answer

    Decode first, and answer DECERR without starting any APB transfer, because APB itself defines no decode error. With no PSELx asserted, nobody drives PREADY. So a transfer started to a hole never completes, unless a default responder answers it. DECERR also tells software that the address was wrong. SLVERR would instead suggest that a peripheral refused it.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer decodes the address before starting any APB transfer, and returns DECERR for a hole.

  13. What IfTimeouts in an APB BridgeL3 SeniorL4 Staff

    A completer hangs with PREADY low. Should the bridge time out? What does it return, and what is the risk?

    Reveal the Model Answer

    A timeout is system policy, not protocol. After a programmed limit, the bridge returns SLVERR so the CPU is not stuck forever. The risk is on the APB side: the requester must hold the transfer until PREADY, so the bridge cannot legally abandon it. It either keeps that segment blocked and fails every later access, or resets the completer. Specify which, raise an interrupt, and verify that recovery path.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Senior)

    A good senior answer separates the AXI response from the stuck APB transfer. It knows the bridge cannot simply drop an APB access that has started.

  14. ComparePSLVERR Through an AXI BridgeL2 Mid-LevelL3 Senior

    How does PSLVERR reach an AXI manager through a bridge? A 4-beat AXI write becomes four APB transfers and the second gets PSLVERR. What does the manager see?

    Reveal the Model Answer

    The bridge maps PSLVERR to SLVERR, in the RRESP of the failing beat for a read and in BRESP for a write. A write has one completion response for the whole transaction. So the bridge must merge four APB results into one BRESP. Reporting SLVERR if any beat failed is the usual choice. The remaining beats still run: AXI never shortens a burst, and every read beat is returned whatever its response.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer knows AXI reads report a response per beat but writes report once. So the bridge must merge the four APB results into one.

  15. Scale ItHow You Know the Bridge Is DoneL3 SeniorL4 Staff

    Walk me through your verification bench for an AXI-to-APB bridge, and tell me how you know you are done.

    Reveal the Model Answer

    Protocol checkers on both ports catch rule breaks. An end-to-end scoreboard predicts the APB transfers (one per beat, with address, PSTRB and PPROT) and the AXI responses. Done means every check passes and the coverage model is closed. That model crosses burst type, length and size with unaligned and narrow beats and wait states. It also covers PSLVERR on the first, middle and last beat, unmapped addresses, and reads racing writes.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Senior)

    A good senior answer names protocol checkers on both sides plus a scoreboard that predicts results. It gives a concrete coverage cross.

  16. Break ItSigning off APB Error HandlingL2 Mid-LevelL3 Senior

    What would you check and cover before you sign off error handling on an APB peripheral?

    Reveal the Model Answer

    Check that each refused access errors: a write to read-only, an unmapped offset, or a wrong size or protection. Check that PSLVERR is read only at completion, and that register state after a failed write matches the documented policy. Cover read and write, crossed with error or not, crossed with zero, one and many wait states. Also cover an error followed straight by a good transfer to the same completer. Then check the error reaches software through the bridge.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer lists the causes of an error. It crosses read or write, error or not, and the number of wait states in coverage.

  17. Prove ItSolve P3.7.1: The Bridge's APB SideSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P3.7.1

  18. Prove ItSolve P3.6.1: Decoder and Read MuxSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P3.6.1

  19. Prove ItSolve P3.2.1: An APB Register BlockSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P3.2.1

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

The completer can perform the write as soon as it sees PSEL and PWRITE high.

PSEL is high in every cycle of the transfer. A completer that acts whenever it is selected acts in SETUP and again in each ACCESS cycle. So a FIFO push or a counter repeats once per wait state.

Run It
RUNIcarus Verilog · in your browser
Edit the code, then run it

        
Expected: FAIL act_on_sel: one write with 0 wait state(s) acted 2 time(s) PASS act_on_done: one write with 0 wait state(s) acted 1 time(s) FAIL act_on_sel: one write with 2 wait state(s) acted 4 time(s) PASS act_on_done: one write with 2 wait state(s) acted 1 time(s)

        
        
      

    

  

    
Spec Misquote

    
PREADY must be low during the SETUP cycle.

    
PREADY may take any value while PENABLE is low. That is exactly what lets a completer with a fixed two-cycle access tie PREADY high. A checker that demands PREADY low in SETUP rejects legal designs.

    
Source AMBA APB Protocol Specification IHI 0024E §3.1.2 With wait states

  

    
Spec Misquote

    
For back-to-back transfers the requester can keep PENABLE high and skip the setup cycle.

    
SETUP always lasts exactly one cycle with PENABLE low. From ACCESS the bus may go straight to SETUP, never straight to another ACCESS.

    
Source AMBA APB Protocol Specification IHI 0024E §4.1 Operating states

  

    
Learn It, Then Prove It