Interview Question · Design
Why Registers Live on APB
The Question
The interviewer asks
Your SoC already has an AXI interconnect. Why put the UART, timer and GPIO registers behind an APB bridge, instead of giving each one an AXI port?
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Reveal the Model Answer
Register traffic is rare, small and tolerant of latency, so APB's simplicity wins. It runs one transfer at a time, with no bursts and no IDs. Each peripheral needs only a tiny state machine, and there are few wires to route. One bridge pays the AXI cost once for many peripherals. The price is throughput: at least two cycles per transfer, and one slow completer stalls the whole APB segment. So blocks that move real data stay on AXI or AHB.
- System bus
The store leaves the processor as a write on the system bus.
Follow the calls, values and waits
- data store: Processor → Interconnect
- To the bridge
The interconnect decodes the address into the APB region and passes the write to the bridge.
Follow the calls, values and waits
- data store: Interconnect → APB bridge
- One select
The bridge decodes the address again, raises
PSEL1only, and runs one APB transfer. The UART and the GPIO see the same wires and ignore them.Follow the calls, values and waits
- data store: APB bridge → Timer
Read the diagram as text
- Processor: issues a store to the timer
- Interconnect: AXI or AHB
- APB bridge: the one requester
- UART: PSEL0
- Timer: PSEL1
- GPIO: PSEL2
- Processor → Interconnect: write
- Interconnect → APB bridge: APB region
- APB bridge → UART: PSEL0
- APB bridge → Timer: PSEL1
- APB bridge → GPIO: PSEL2
The bridge turns one system-bus write into one APB transfer. Only the timer's select goes high.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Fresher)
A good fresher answer says APB is cheap, low-power and simple. It is meant for peripheral registers and connects to the main bus through a bridge.
What Interviewers Listen For (Junior)
A good junior answer puts numbers on the trade-off: at least two cycles per transfer and one transfer at a time. So one slow peripheral delays every other access behind the bridge.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItCompareScale It
- Why Registers Live on APB
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CompareFrom APB2 to APB5L1 Junior
What did APB3, APB4 and APB5 each add?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
APB3 added wait states and errors, through PREADY and PSLVERR. APB4 added protection and sparse writes, through PPROT and PSTRB. APB5 added wake-up signalling, user signals and parity protection. The current issue also adds Realm Management Extension support as an option. An APB2 completer has neither PREADY nor PSLVERR, so a bridge ties them off for it.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer places PREADY and PSLVERR in APB3, and PPROT and PSTRB in APB4.
What Interviewers Listen For (Mid-Level)
A good mid-level answer knows how to connect parts of different versions. For example, a completer with PSTRB behind a requester without it gets PSTRB tied to PWRITE.
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What IfOne Slow Peripheral on the APB SegmentL2 Mid-LevelL3 Senior
One peripheral on your APB segment takes 50 wait states for some registers. What happens to the other peripherals, and what would you do about it?
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Reveal the Model Answer
Every access behind that bridge waits, because APB carries one transfer at a time and nothing starts until the waiting one completes. One fix is to give the slow peripheral its own APB segment or bridge. Another is to make it answer at once with a busy bit that software polls. A third is posted writes: the bridge answers before APB finishes, so it loses PSLVERR for those writes. Pick by the latency budget of the time-critical peripherals.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains that one slow transfer blocks everything behind it, because APB carries one transfer at a time.
What Interviewers Listen For (Senior)
A good senior answer weighs the fixes. A separate segment costs a bridge, polling moves work to firmware, and posted writes lose error reports. It picks one by a latency need, such as an interrupt handler's register reads.
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Scale ItDesigning an AXI-to-APB BridgeL3 SeniorL4 Staff
Design an AXI4-to-APB bridge. What must it do, which decisions are yours, and how would you verify it?
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Reveal the Model Answer
The bridge is the AXI subordinate and the APB requester. It decodes PSELx and makes one APB transfer per AXI beat. Each transfer uses the aligned address, with WSTRB on PSTRB and AxPROT on PPROT. It maps PSLVERR to SLVERR: per beat in RRESP, and merged into the single BRESP. Your decisions are read/write arbitration, DECERR for unmapped addresses, a timeout policy and posted writes. Verify it with checkers on both sides and an end-to-end scoreboard.
A 2-beat AXI Write Through the BridgeMeasured on the bench: cycle 0 is edge 3, where AW is taken; B is sent at edge 10. All cyclesPills: an AXI beat taken by the bridge, then the same data written on APB.
- Cycle 0
AW is taken: a 2-beat write of words at 0x10.
- Cycle 1
Beat 0 is taken from W. The bridge has room for one beat only.
- Cycle 2
APB setup for 0x10 with 11111111. Beat 1 is already offered on W and must wait:
wreadyis 0. - Cycle 3
APB access with
pready1: the first word is written. - Cycle 4
Now the bridge takes beat 1.
- Cycle 5
Setup for 0x14 with 22222222.
- Cycle 6
The second word is written. That was the last beat.
- Cycle 7
B is sent with OKAY: one response for the whole AXI write.
Three edges per beat here: take the W beat, APB setup, APB access. The AXI side could have moved a beat on every edge.
AXI side APB side Note One burst of N beats N transfers, each SETUP + ACCESS APB has no burst signals; the bridge computes each beat's address Beat address (maybe unaligned) Aligned PADDR An unaligned PADDR is UNPREDICTABLE; the strobes pick the bytes WSTRB of the beat PSTRB All PSTRB low on reads AxPROT PPROT Same three bit meanings: privileged, non-secure, instruction RRESP per beat, one BRESP PSLVERR per transfer Merging writes is a bridge decision Address with no completer No transfer Answer DECERR What the bridge translates. The table is ours; each row is sourced in review.claims.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer covers one APB transfer per beat, aligned PADDR with strobes, PPROT, the response mapping and merge, and DECERR. It keeps the AXI rules: every read beat comes back, and one BRESP follows the last W beat.
What Interviewers Listen For (Staff)
A good staff answer frames the architecture: the ACLK to PCLK ratio and the number of APB segments. It weighs posted writes against error reports and adds a security filter on PPROT[1]. It weighs timeouts against APB's rule that an access cannot be dropped. It defines sign-off with checkers on both ports, a predicting scoreboard and a full coverage model.
Misconception
Pass the burst start address to APB and let the peripheral increment it.
APB has no length or burst signal, so every transfer stands alone. The bridge must compute each beat's address from the AXI burst rules. It then issues one APB transfer per beat.
Source AMBA APB Protocol Specification IHI 0024E §2.1 AMBA APB signals (Table 2-1 has no burst or length signal); lesson P3.7 (a 4-beat burst becomes four APB transfers)
Spec Misquote
On PSLVERR in the middle of a read burst, stop and return the error at once.
AXI requires every read data transfer of the burst to be returned, whatever the response. A write gets exactly one completion response. Stopping early breaks the AXI side.
Source AMBA AXI Protocol Specification IHI 0022L §A3.3.2 Read response; §A3.3.1 Write response
Missed Corner
Send the unaligned AXI byte address straight to PADDR.
An unaligned PADDR is permitted, but its result is UNPREDICTABLE: the completer may use it, align it or error. Send the aligned word address, and select the bytes with PSTRB.
Source AMBA APB Protocol Specification IHI 0024E §2.1.1 Address bus
- Cycle 0
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WhyUnmapped Addresses Behind an APB BridgeL2 Mid-LevelL3 Senior
What should the bridge answer for an address that no APB completer owns? Why not just start the APB transfer anyway?
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Reveal the Model Answer
Decode first, and answer DECERR without starting any APB transfer, because APB itself defines no decode error. With no PSELx asserted, nobody drives PREADY. So a transfer started to a hole never completes, unless a default responder answers it. DECERR also tells software that the address was wrong. SLVERR would instead suggest that a peripheral refused it.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer decodes the address before starting any APB transfer, and returns DECERR for a hole.
What Interviewers Listen For (Senior)
A good senior answer separates DECERR, where no end point exists, from SLVERR, where an end point refused. It covers every hole and every region edge in the address map.
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What IfTimeouts in an APB BridgeL3 SeniorL4 Staff
A completer hangs with PREADY low. Should the bridge time out? What does it return, and what is the risk?
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Reveal the Model Answer
A timeout is system policy, not protocol. After a programmed limit, the bridge returns SLVERR so the CPU is not stuck forever. The risk is on the APB side: the requester must hold the transfer until PREADY, so the bridge cannot legally abandon it. It either keeps that segment blocked and fails every later access, or resets the completer. Specify which, raise an interrupt, and verify that recovery path.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer separates the AXI response from the stuck APB transfer. It knows the bridge cannot simply drop an APB access that has started.
What Interviewers Listen For (Staff)
A good staff answer makes it an architecture decision. It decides where timeouts live, how a hung peripheral is reset, and how software finds out. It adds an error-injection test to the verification plan.
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ComparePSLVERR Through an AXI BridgeL2 Mid-LevelL3 Senior
How does PSLVERR reach an AXI manager through a bridge? A 4-beat AXI write becomes four APB transfers and the second gets PSLVERR. What does the manager see?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The bridge maps PSLVERR to SLVERR, in the RRESP of the failing beat for a read and in BRESP for a write. A write has one completion response for the whole transaction. So the bridge must merge four APB results into one BRESP. Reporting SLVERR if any beat failed is the usual choice. The remaining beats still run: AXI never shortens a burst, and every read beat is returned whatever its response.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer knows AXI reads report a response per beat but writes report once. So the bridge must merge the four APB results into one.
What Interviewers Listen For (Senior)
A good senior answer calls the merge rule a design decision that must be documented. It asks whether later beats should still be written after a failure. It checks that the read side still returns every beat after an error.
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Scale ItHow You Know the Bridge Is DoneL3 SeniorL4 Staff
Walk me through your verification bench for an AXI-to-APB bridge, and tell me how you know you are done.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Protocol checkers on both ports catch rule breaks. An end-to-end scoreboard predicts the APB transfers (one per beat, with address, PSTRB and PPROT) and the AXI responses. Done means every check passes and the coverage model is closed. That model crosses burst type, length and size with unaligned and narrow beats and wait states. It also covers PSLVERR on the first, middle and last beat, unmapped addresses, and reads racing writes.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer names protocol checkers on both sides plus a scoreboard that predicts results. It gives a concrete coverage cross.
What Interviewers Listen For (Staff)
A good staff answer adds what this bench misses: performance, an unusual clock ratio, and reset during a transfer. It says how each is covered, such as a directed test or formal on the decoder. It states the exit rule before work starts.
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Break ItSigning off APB Error HandlingL2 Mid-LevelL3 Senior
What would you check and cover before you sign off error handling on an APB peripheral?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Check that each refused access errors: a write to read-only, an unmapped offset, or a wrong size or protection. Check that PSLVERR is read only at completion, and that register state after a failed write matches the documented policy. Cover read and write, crossed with error or not, crossed with zero, one and many wait states. Also cover an error followed straight by a good transfer to the same completer. Then check the error reaches software through the bridge.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer lists the causes of an error. It crosses read or write, error or not, and the number of wait states in coverage.
What Interviewers Listen For (Senior)
A good senior answer adds the path to software, through BRESP or RRESP and an interrupt or status bit. It also tests a good transfer right after an error. Its exit rule: every documented refusal is hit in each wait class.
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Prove ItSolve P3.7.1: The Bridge's APB SideSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Prove ItSolve P3.6.1: Decoder and Read MuxSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Misconception
APB is chosen because it has lower latency than AXI.
APB is chosen for low cost and low complexity. Every transfer takes at least two cycles, and nothing overlaps. A register access through a bridge is slower, not faster.
Source AMBA APB Protocol Specification IHI 0024E §1.1 About the APB protocol
Half-Truth
APB is just AXI4-Lite with a different name.
AXI4-Lite keeps independent read and write channels, each with its own valid/ready handshake. APB shares one address and control path. Its read and write data cannot move at the same time.