Interview Question · Concept
The Five AXI Channels
- Likely at NVIDIA
- Likely at Microchip
- Likely at Broadcom
The Question
The interviewer asks
AXI has five channels. Name them, say who drives each, and tell me why reads and writes are kept apart.
You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
AW, W and B carry writes; AR and R carry reads. The manager drives AW, W and AR, and the subordinate drives B and R. Each channel has its own valid/ready handshake. The split lets a read and a write be in flight at once. It also lets write data move independently of its address. And you can add a register slice (a pipeline stage) to any one channel alone.
A lit wire carries a 1 on its VALID. A pill is a transfer in that cycle.
- Cycle 1
Reset is active until after edge 1: every VALID is low, and the memory keeps its READYs low too.
- Cycle 2
Reset is over. After this edge the memory raises every READY: it can take a request on any channel.
- Cycle 3
The write address moves on AW: address 0x1000, two beats of four bytes, id 1.
- Cycle 4
Two channels in one cycle: the first write beat on W, and a read address on AR. Nothing waited for anything.
- Cycle 5
The second write beat, flagged as the last one. The write data is complete; the response is still to come.
- Cycle 7
The first read beat arrives on R before the write has been answered. Reads and writes are independent.
- Cycle 8
The write response on B and the last read beat on R, in the same cycle. One write, one read, five channels, seven cycles.
Measured on the bench of this lesson. Five handshakes, two transactions, no channel waiting on another.
| Channel | Driven by | Carries | Per transaction |
|---|---|---|---|
| AW | manager | write address and attributes | one transfer |
| W | manager | write data, WSTRB, WLAST | AWLEN + 1 transfers |
| B | subordinate | write response, BID | one completion response |
| AR | manager | read address and attributes | one transfer |
| R | subordinate | read data, RRESP per beat, RLAST, RID | ARLEN + 1 transfers |
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Fresher)
A good fresher answer names all five channels and who drives each one. It says a transfer happens at a rising edge where VALID and READY are both high.
What Interviewers Listen For (Junior)
A good junior answer explains the only links between channels. Inside a transaction, B follows the last W beat and the AW, and R follows AR. Responses with the same ID are also tied in order.
What Interviewers Listen For (Senior)
A good senior answer links the split to timing closure. Any channel can get its own register slices, because no fixed timing ties the channels together.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItCompareScale It
- The Five AXI Channels
-
WhyWhy Writes Need a B ChannelL0 FresherL1 Junior
Why not just let the write finish when the last data beat is accepted? What does B give you?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Accepting a beat only means the next stage had room, not that the write reached its target or succeeded. B is the completion response, and it carries the error code. The subordinate sends it only after it has the address and the last beat. For a Non-bufferable write, B also guarantees the write is visible to any manager. A manager that needs ordering waits for B.
One Write: An Address, Four Beats, One ResponseA four-beat write of four bytes per beat to 0x100. The memory takes every transfer in the cycle it is offered. All cyclesThe slots of the memory fill one beat at a time; the response comes only when all four are in.
- Cycle 3
The address transfer: 0x100,
AWLEN= 3 (four beats),AWSIZE= 2 (four bytes each),AWBURST= INCR, id 1. - Cycle 4
Beat 0 on W. The strobes say which byte lanes carry data; here all four.
- Cycle 6
Beats 1 and 2 followed in consecutive cycles because
WREADYstayed high. - Cycle 7
Beat 3 carries
WLAST: the manager says this is the final beat of the burst.AWLENsaid four, and this is the fourth. - Cycle 10
The response, three edges later on this bench: one
BVALID, oneBRESPof OKAY, withBID= 1 so the manager knows which write it answers.
Measured on the bench. One transaction, six transfers: one on AW, four on W, one on B.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Fresher)
A good fresher answer says B reports whether the whole write succeeded or failed.
What Interviewers Listen For (Mid-Level)
A good mid-level answer says B is how the manager orders its accesses. A later access that must see the write waits for B first.
- Cycle 3
-
What IfA Read Issued Before the Write ResponseL1 JuniorL2 Mid-Level
A manager writes a word, and right after its last W beat it reads the same address with the same ID. Is it guaranteed to see the new value?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
No. AXI never orders a read against a write, whatever the IDs, so the read may return the old value. The manager's tool is to wait for the write's B response before issuing the read. Lesson P2.12 measured exactly this, with a posted write and a six-cycle write latency. The read issued after the last data beat returned the old word.
Self-Check
Tick each key point you covered in your answer.
Misconception
"Same ID means same ordering stream, so the read waits for the write."
Same-ID ordering applies within reads and within writes. Read and write channels have no ordering guarantee between them.
Source AMBA AXI Protocol Specification IHI 0022L §A5.3 Request ordering
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Scale ItOrdering a Flag After a BufferL2 Mid-LevelL3 Senior
A DMA writes a 4 KB buffer, then writes a "done" flag that the CPU polls. How do you make sure the CPU never sees the flag before the data?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Before writing the flag, wait for the B responses of every buffer write. Only a completion response makes an access observable. Same-ID writes stay in order only to the same location, so one ID does not order the buffer against the flag. A Bufferable B can come from a buffer partway along the path. It then guarantees observability only inside the write's Domain, so the CPU must sit in that Domain.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer says the manager must wait for every B response before it writes the flag.
What Interviewers Listen For (Senior)
A good senior answer adds the Bufferable case. An early response from a buffer on the way only guarantees visibility inside the Domain. It also says one ID does not order writes to different addresses.
-
Prove ItSolve P2.12.1: The Stale ReadSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
What IfA Read Issued Before the Write ResponseL1 JuniorL2 Mid-Level
A manager writes a word, and right after its last W beat it reads the same address with the same ID. Is it guaranteed to see the new value?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
No. AXI never orders a read against a write, whatever the IDs, so the read may return the old value. The manager's tool is to wait for the write's B response before issuing the read. Lesson P2.12 measured exactly this, with a posted write and a six-cycle write latency. The read issued after the last data beat returned the old word.
Self-Check
Tick each key point you covered in your answer.
Misconception
"Same ID means same ordering stream, so the read waits for the write."
Same-ID ordering applies within reads and within writes. Read and write channels have no ordering guarantee between them.
Source AMBA AXI Protocol Specification IHI 0022L §A5.3 Request ordering
-
Scale ItOrdering a Flag After a BufferL2 Mid-LevelL3 Senior
A DMA writes a 4 KB buffer, then writes a "done" flag that the CPU polls. How do you make sure the CPU never sees the flag before the data?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Before writing the flag, wait for the B responses of every buffer write. Only a completion response makes an access observable. Same-ID writes stay in order only to the same location, so one ID does not order the buffer against the flag. A Bufferable B can come from a buffer partway along the path. It then guarantees observability only inside the write's Domain, so the CPU must sit in that Domain.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer says the manager must wait for every B response before it writes the flag.
What Interviewers Listen For (Senior)
A good senior answer adds the Bufferable case. An early response from a buffer on the way only guarantees visibility inside the Domain. It also says one ID does not order writes to different addresses.
-
Prove ItSolve P2.12.1: The Stale ReadSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
CompareFive Channels Against One Shared BusL1 Junior
APB moves one transfer at a time over one set of wires. What does AXI gain with its five channels, and what does it cost?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
AXI gains concurrency: reads and writes overlap, and many transactions can be outstanding (issued but not yet finished). Each channel can also be pipelined on its own. APB is not pipelined, and every transfer takes at least two cycles. The cost is wires and logic: five handshakes, ID tracking, reorder buffers and a much harder verification job. That is why register blocks often sit on APB or AXI4-Lite.
Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve P2.2.1: Catch the Broken ManagersSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Misconception
"There are four channels: read address, read data, write address, write data."
Forgets B. A write must be acknowledged, and the response must come after the last data beat. Without B, the manager cannot know whether a write completed or failed.
Source AMBA AXI Protocol Specification IHI 0022L §A2.3.2 Dependencies between channel handshake signals; §A3.3.1 Write response
Spec Misquote
"The read response comes on its own channel, like B."
Read responses ride on R, one RRESP with every data beat. Only writes have a separate response channel.
Source AMBA AXI Protocol Specification IHI 0022L §A3.3.2 Read response