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The Scoreboard That Fails Legal Traffic

L2 Mid-LevelL3 Senioraxiverificationidsscoreboard

The Question

The interviewer asks

Your AXI scoreboard pushes each read's expected data into one queue at AR time. It pops the queue on every R beat. It passes against a simple memory but fails on the new interconnect, with no protocol errors. What is wrong?

systemverilog
// One global expected-data queue
if (arvalid && arready) expected.push_back(model_read(araddr));
if (rvalid && rready) begin
  exp = expected.pop_front();
  assert (rdata == exp);
end
Reveal the Model Answer

The scoreboard assumes responses return in issue order. The new fabric returns different IDs out of order, which is legal. So the expected and actual streams no longer line up. Key the expected queue by ID: one in-order queue per RID, popped when that ID's beat arrives. The twin shows the in-order version reporting two mismatches on legal traffic. The per-ID version still catches a real same-ID swap.

Ten Read Beats, Three IDs, Four TransactionsThe memory answers with reordering and interleaving on. The monitor files every beat under the oldest open read with its RID.
Rrid 1rid 2rid 3Memoryreorder, interleaveMonitorfiles by RIDopen read, id 1open read, id 2open read, id 3

Each slot row is the oldest open read of one ID. A beat with RLAST completes it; a full row empties into a finished transaction.

0123456789clkrvalidrreadyrid23123121rdataa0a1a2b0a2a3b1a0a3a1rlastis1is2is3m100000001001100010011m200010011011111110000m30000000100110000
  1. Cycle 2

    Two beats of id 2, then a beat of id 3. The read of id 2 is still open; the monitor has three transactions filling at once.

  2. Cycle 5

    The beat of id 3 carries RLAST: the 2-beat read of 0x108 is complete and is published first, although it was requested last.

  3. Cycle 6

    Id 1 completes next with b0 b1: the slow read of 0x4000. Id 2's four beats are still arriving between the others.

  4. Cycle 9

    The last two beats finish id 2 and then id 1's second read. Four transactions out of ten interleaved beats, none of them confused.

Measured. Ten read beats from four reads arrive out of order. Each beat belongs to the oldest open read with its RID.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Mid-Level)

A good mid-level answer spots that the scoreboard assumes issue order. It fixes this with one queue per ID.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

What IfProve ItBreak ItScale It

  1. The Scoreboard That Fails Legal Traffic
  2. Break ItThe Reorder No Checker SeesL2 Mid-LevelL3 Senior

    A subordinate swaps two same-ID reads. When does your protocol checker catch it, and when not?

    Reveal the Model Answer

    Only when the two reads have different lengths, because the first response's RLAST then lands on the wrong beat count. If the lengths are equal, every beat is legal on the wires, and only the data shows the swap. You need a scoreboard keyed by ID that knows which address each read asked for. Lessons P2.10 and P2.18 measured exactly this split.

    Two Reads, One ID, and a Fabric That Lets the Fast One PassThe manager asks m1 (slow) then m0 (fast) with the same ID. With ordering off, the fabric forwards both at once and hands back whatever answers first.
    ARRARRARRManagertwo reads, id 5Fabricordering offm0, fast0x0000 to 0x7fffm1, slow0x8000 to 0xffff

    Both requests carry id 5. The manager can only file the first data that comes back under its oldest request with that ID.

    012345678910clkarvalidarreadyaraddr8100104xar_m1a1x8100xar_m0a0x104xr_m0d0xa1a2xr_m1d1xb0b1xrvalidrreadyridx5x5rdataxa1a2xb0b1rlast
    1. Cycle 1

      The second request, to the fast m0, is accepted one cycle after the first. A fabric that enforces ordering would hold it until the slow read had answered. This one forwards it at once.

    2. Cycle 6

      m0 answers first, and the fabric passes a1 to the manager under rid 5. The manager's oldest request with id 5 is the read of 0x8100, so a1 is filed as the first word of 0x8100.

    3. Cycle 9

      Now m1 answers. b0 and b1, the real content of 0x8100, are filed as the read of 0x104. Every handshake was legal; two transactions swapped their data.

    Measured through a fabric with ordering off. Two same-ID reads swap their data, and every handshake is legal.

    Self-Check

    Tick each key point you covered in your answer.

  3. What IfInterleaved Read DataL2 Mid-Level

    Two 4-beat reads on IDs 1 and 2 come back as 1, 2, 1, 2, 2, 1, 2, 1. Legal? What must the monitor do?

    Reveal the Model Answer

    Legal: different IDs may interleave beat by beat. Each transaction's beats must still stay in order and end with its own RLAST. The monitor must assemble beats per RID and file each beat under the oldest open read of that ID. It closes the transaction on RLAST. A monitor that assumes contiguous bursts glues beats of different reads together.

    Self-Check

    Tick each key point you covered in your answer.

  4. What IfA Manager That Cannot Take InterleavingL2 Mid-LevelL3 Senior

    A manager team says their block cannot handle interleaved read data. Is that allowed, and what does the spec offer?

    Reveal the Model Answer

    Not if the manager issues different IDs: such a manager must accept interleaved data. The Read_Interleaving_Disabled property only lets it switch interleaving off as an optimisation. That works only when the attached subordinate supports it. So the test plan must cover interleaved returns for every manager that uses several IDs.

    Self-Check

    Tick each key point you covered in your answer.

    Spec Misquote

    "Interleaving is optional, so our manager need not handle it."

    Every manager that issues different IDs must accept it. Disabling it is an optimisation that needs the subordinate to support it.

    Source AMBA AXI Protocol Specification IHI 0022L §A5.6.1 Read data interleaving

  5. Scale ItFunctional Coverage for an AXI PortL3 Senior

    What goes in the functional coverage of an AXI subordinate before you call it done?

    Reveal the Model Answer

    Group it by channel handshakes, requests, data, responses and ordering, as in the table. The corners that matter most are bursts ending exactly at 4 KB and errors mid-burst. So do maximum outstanding depth, cross-ID reordering and W before AW. Cross only the pairs the design can actually produce, and close holes with directed tests.

    GroupItems
    HandshakeREADY before/with/after VALID on each channel; stalls of 0, 1, many cycles
    RequestFIXED/INCR/WRAP × length class × size; unaligned start; narrow; ends at 4 KB
    Datasparse and all-zero strobes; first-beat partial strobes
    ResponseOKAY, SLVERR, DECERR (and EXOKAY if supported); error on a middle beat
    Orderingmax outstanding reached; cross-ID reorder; read interleave; W before AW; same ID back to back

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Senior)

    A good senior answer organises coverage by channel handshakes, requests, responses and ordering. It crosses only the cases the design can really produce.

  6. Prove ItSolve P2.11.1: An ID-Keyed ScoreboardSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P2.11.1

  7. Prove ItSolve P2.18.5: The Subordinate That ReorderedSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P2.18.5

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"The interconnect is reordering responses, so it is the bug."

Reordering across IDs is allowed. In the twin, legal reordering of IDs 1 and 2 gives the in-order scoreboard 2 mismatches and the per-ID one 0. Both catch an illegal swap within ID 3.

Run It

The in-order scoreboard complains about legal traffic. The per-ID scoreboard is silent on it and still catches the illegal same-ID swap.

RUNVerilator · simulator service
Edit the code, then run it
Expected: FAIL legal reorder across IDs 1 and 2: 2 mismatches PASS illegal swap within ID 3: 2 mismatches
See the Fix
module tb;
  localparam bit BUGGY = 0;   // 1: one expected queue in issue order; 0: one queue per ARID
  logic [31:0] in_order[$];
  logic [31:0] by_id[4][$];
  int bad;
  function automatic void issue(int id, logic [31:0] expect_data);
    if (BUGGY) in_order.push_back(expect_data); else by_id[id].push_back(expect_data);
  endfunction
  function automatic void response(int id, logic [31:0] data);     // one single-beat R response
    logic [31:0] e = BUGGY ? in_order.pop_front() : by_id[id].pop_front();
    if (data !== e) bad++;
  endfunction
  task automatic report(string what, bit is_legal);
    // A scoreboard is right when it is silent on legal traffic and complains on illegal traffic.
    $display("%s %s: %0d mismatches", ((bad == 0) == is_legal) ? "PASS" : "FAIL", what, bad);
    bad = 0;
  endtask
  initial begin
    issue(1, 32'hA1); issue(2, 32'hB2);
    response(2, 32'hB2); response(1, 32'hA1);       // different IDs answered out of order: legal
    report("legal reorder across IDs 1 and 2", 1);
    issue(3, 32'hC3); issue(3, 32'hC4);
    response(3, 32'hC4); response(3, 32'hC3);       // same ID swapped: illegal
    report("illegal swap within ID 3", 0);
    $finish;
  end
endmodule

Prints: PASS legal reorder across IDs 1 and 2: 0 mismatches PASS illegal swap within ID 3: 2 mismatches

Wrong Altitude

"Turn off reordering in the interconnect and the test passes."

That hides the bench bug and stops testing the fabric in the mode it ships in. Fix the model, not the DUT configuration.

Learn It, Then Prove It