Interview Question · Debug

The Link That Never Moved

L0 FresherL1 Juniorhandshakedeadlockdebug

The interviewer asks

A DMA engine and a memory controller each pass their unit tests. Connected, nothing moves: the wave shows valid and ready low forever while both have work. What happened and whose bug is it?

log

Illustrative clock samples
edge  source_has_data  sink_has_room  valid  ready
1     1                1              0      0
2     1                1              0      0
3     1                1              0      0

Reveal the Model Answer

It is a circular wait. The engine raises valid only after seeing ready, and the controller raises ready only after seeing valid. The controller is legal, because a sink may wait for valid. The engine broke the rule that valid must not wait for ready. Its unit test passed because that bench kept ready high in advance. The run shows the same source moving 18 beats with one legal sink and 0 with another.

Two Polite Blocks and a Bus That Never MovesThe source has a beat and the sink has room, yet each waits for the other's first move.

Both blocks wait. Neither wire ever lights, so no beat ever moves.

Cycle 0
The engine holds beat a1. It will raise valid as soon as it sees ready.
Cycle 1
The controller has four free slots. It will raise ready as soon as it sees valid.
Cycle 4
Four edges later nothing has changed, and nothing ever will. A rule about who moves first is the only cure.

Each block waits for the other to move first, so neither ever moves. The source broke the rule.

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Edit the code, then run it

Expected: bad source, waiting sink: 0 beats in 20 cycles bad source, ready-first sink: 18 beats in 20 cycles good source, waiting sink: 18 beats in 20 cycles

// Two blocks that each pass a unit test. The source waits for ready before raising valid
// (illegal); sink A waits for valid before raising ready (legal); sink B keeps ready high.
module tb;
  logic clk = 0;
  always #5 clk = ~clk;
  int moved [3];
  for (genvar p = 0; p < 3; p++) begin : pair
    // p=0: bad source + waiting sink, p=1: bad source + ready-first sink, p=2: good source + waiting sink
    logic valid = 0, ready = 0;
    always @(posedge clk) begin
      // the source has a beat every cycle
      if (p == 2) valid <= 1;                 // legal: offer as soon as there is data
      else        valid <= ready;             // illegal: valid waits for ready
      // the sink always has room
      if (p == 1) ready <= 1;                 // ready in advance
      else        ready <= valid;             // legal: ready waits for valid
      if (valid && ready) moved[p]++;
    end
  end
  initial begin
    repeat (20) @(posedge clk);
    #1;
    $display("bad source,  waiting sink:     %0d beats in 20 cycles", moved[0]);
    $display("bad source,  ready-first sink: %0d beats in 20 cycles", moved[1]);
    $display("good source, waiting sink:     %0d beats in 20 cycles", moved[2]);
    $finish;
  end
endmodule

Self-Check

Tick each key point you covered in your answer.

Key point 1 It is a circular wait. Key point 2 The engine raises valid only after seeing ready, and the controller raises ready only after seeing valid. Key point 3 The controller is legal, because a sink may wait for valid. Key point 4 The engine broke the rule that valid must not wait for ready. Key point 5 Its unit test passed because that bench kept ready high in advance. Key point 6 The run shows the same source moving 18 beats with one legal sink and 0 with another.

What Interviewers Listen For (Fresher)

A good fresher answer sees that each block waits for the other, so neither moves. It names the rule the source broke: valid must not wait for ready.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompareScale It

The Link That Never Moved
WhyWhy the Rule Is LopsidedL1 JuniorL2 Mid-Level
Why is the sink allowed to wait for valid, but the source is not allowed to wait for ready?

Reveal the Model Answer

Someone has to move first, and the source is the side that knows a beat exists. Letting the sink wait is useful. An interconnect can decode the address carried with valid before it decides which target grants it. A sink can also keep ready low to save power. If either side could wait, two compliant blocks could deadlock, so the spec fixes the order.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Someone has to move first, and the source is the side that knows a beat exists. Key point 2 Letting the sink wait is useful. Key point 3 An interconnect can decode the address carried with valid before it decides which target grants it. Key point 4 A sink can also keep ready low to save power. Key point 5 If either side could wait, two compliant blocks could deadlock, so the spec fixes the order.

What Interviewers Listen For (Junior)
A good junior answer says one side has to move first, or two waiting blocks can stop each other.
- Lesson P1.3Handshakes: Request and Acknowledge, Valid and Ready
CompareReady as a Function of ValidL2 Mid-LevelL3 Senior
If the sink may wait for valid, may it compute ready combinationally from valid in the same cycle?

Reveal the Model Answer

Inside one block, a same-cycle ready = f(valid) works logically. But on an AXI interface, the spec forbids combinational paths from inputs to outputs. So the wait goes through a register, and ready rises the cycle after valid is seen. The rule stops timing paths from chaining across blocks. A combinational ready path would grow with every stage.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Inside one block, a same-cycle ready = f(valid) works logically. Key point 2 But on an AXI interface, the spec forbids combinational paths from inputs to outputs. Key point 3 So the wait goes through a register, and ready rises the cycle after valid is seen. Key point 4 The rule stops timing paths from chaining across blocks. Key point 5 A combinational ready path would grow with every stage.

What Interviewers Listen For (Mid-Level)
A good mid-level answer knows that AXI bans a combinational path from an input to an output on an interface.

Spec Misquote

"Waiting for valid means ready can be assign ready = valid && !full; at the port."

That is an input-to-output combinational path at the interface, which AXI forbids. Register it, or decouple it with a slice.

Source AMBA AXI Protocol Specification IHI 0022L §A2.1.1 Clock
Prove ItSolve R4.4.1: A Skid BufferSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem R4.4.1
Break ItTwo Blocks That Close a Combinational LoopL2 Mid-LevelL3 Senior
Break it: one block makes valid from ready, and its neighbour makes ready from valid, both in the same cycle. What happens?

Reveal the Model Answer

The two paths close a combinational loop through both blocks. Simulation can oscillate or hang in zero time, and timing tools cut the loop at a random point. AXI rules both halves out. A transmitter must not wait for READY before it asserts VALID, and no input may reach an output combinationally.

Self-Check
Tick each key point you covered in your answer.
Key point 1 The two paths close a combinational loop through both blocks. Key point 2 Simulation can oscillate or hang in zero time, and timing tools cut the loop at a random point. Key point 3 AXI rules both halves out. Key point 4 A transmitter must not wait for READY before it asserts VALID, and no input may reach an output combinationally.

Missed Corner

"Each block is fine on its own, so the pair is fine."

The loop exists only when they connect. Check each interface rule at the block, or the loop appears at integration.

Source AMBA AXI Protocol Specification IHI 0022L §A2.1.1 Clock
- Lesson P2.2The Handshake, the Clock and Reset, AXI Style
- Lesson R4.4Stalls, Backpressure and the Skid Buffer
What IfReady as a Function of ValidL2 Mid-LevelL3 Senior
If the sink may wait for valid, may it compute ready combinationally from valid in the same cycle?

Reveal the Model Answer

Inside one block, a same-cycle ready = f(valid) works logically. But on an AXI interface, the spec forbids combinational paths from inputs to outputs. So the wait goes through a register, and ready rises the cycle after valid is seen. The rule stops timing paths from chaining across blocks. A combinational ready path would grow with every stage.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Inside one block, a same-cycle ready = f(valid) works logically. Key point 2 But on an AXI interface, the spec forbids combinational paths from inputs to outputs. Key point 3 So the wait goes through a register, and ready rises the cycle after valid is seen. Key point 4 The rule stops timing paths from chaining across blocks. Key point 5 A combinational ready path would grow with every stage.

What Interviewers Listen For (Mid-Level)
A good mid-level answer knows that AXI bans a combinational path from an input to an output on an interface.

Spec Misquote

"Waiting for valid means ready can be assign ready = valid && !full; at the port."

That is an input-to-output combinational path at the interface, which AXI forbids. Register it, or decouple it with a slice.

Source AMBA AXI Protocol Specification IHI 0022L §A2.1.1 Clock
Prove ItSolve R4.4.1: A Skid BufferSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem R4.4.1
Break ItTwo Blocks That Close a Combinational LoopL2 Mid-LevelL3 Senior
Break it: one block makes valid from ready, and its neighbour makes ready from valid, both in the same cycle. What happens?

Reveal the Model Answer

The two paths close a combinational loop through both blocks. Simulation can oscillate or hang in zero time, and timing tools cut the loop at a random point. AXI rules both halves out. A transmitter must not wait for READY before it asserts VALID, and no input may reach an output combinationally.

Self-Check
Tick each key point you covered in your answer.
Key point 1 The two paths close a combinational loop through both blocks. Key point 2 Simulation can oscillate or hang in zero time, and timing tools cut the loop at a random point. Key point 3 AXI rules both halves out. Key point 4 A transmitter must not wait for READY before it asserts VALID, and no input may reach an output combinationally.

Missed Corner

"Each block is fine on its own, so the pair is fine."

The loop exists only when they connect. Check each interface rule at the block, or the loop appears at integration.

Source AMBA AXI Protocol Specification IHI 0022L §A2.1.1 Clock
- Lesson P2.2The Handshake, the Clock and Reset, AXI Style
- Lesson R4.4Stalls, Backpressure and the Skid Buffer
Scale ItCatching Circular Waits Before IntegrationL3 Senior
How would your methodology have caught that deadlock at block level, before the two blocks met?

Reveal the Model Answer

Test each source against an adversarial sink, one that keeps ready low until it sees valid. Assert that pending work produces valid within a bound while ready stays low. In every agent, randomise ready per cycle, including long low stretches. In formal, assume ready stays low until valid and prove that valid rises. A cover that never hits points at the circular wait.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Test each source against an adversarial sink, one that keeps ready low until it sees valid. Key point 2 Assert that pending work produces valid within a bound while ready stays low. Key point 3 In every agent, randomise ready per cycle, including long low stretches. Key point 4 In formal, assume ready stays low until valid and prove that valid rises. Key point 5 A cover that never hits points at the circular wait.

What Interviewers Listen For (Senior)
A good senior answer puts a hostile sink, one that keeps ready low until it sees valid, into the reusable agent. It adds a property that valid comes within a bound, not just a global timeout.
Prove ItSolve P1.3.2: Catch the Broken SourcesSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem P1.3.2

What People Get Wrong

Common wrong answers and why they fail.

Half-Truth

"Fix the controller so it raises ready first."

That hides the bug for this pairing only. The run shows the same source deadlocking with any legal sink that waits for valid. One example is an interconnect that decodes the address first.

Wrong Altitude

"Add a watchdog that pulses ready when the link is idle too long."

A watchdog turns a protocol violation into a performance bug that comes and goes. The rule exists so that no timer is needed.

Misconception

"Both blocks are at fault; they need to agree who goes first."

The spec already decides: the receiver may wait, and the transmitter may not. Only the source breaks the spec.

Source AMBA AXI Protocol Specification IHI 0022L §A2.3 Valid-Ready transport

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