Interview Question · Design

Registering Ready Without Losing Beats

L2 Mid-LevelL3 Seniorhandshakepipeliningtiming

The interviewer asks

Timing fails on the ready path through a chain of pipeline stages. A colleague registers ready in each stage. What breaks, and what do you build instead?

Reveal the Model Answer

A registered ready tells the stage about a stall one edge late. So the stage accepts a beat it has nowhere to put, and overwrites one. A slice that accepts only when empty is safe but halves throughput. The fix is a skid buffer: a second register that catches the one beat in flight when the stall arrives. It gives registered ready at full rate, for roughly twice the flops.

A Registered Ready and No Room for the Extra BeatThe producer offers beats 1 to 6. The consumer drops out_ready for edge 5 only. Each column shows the values just before an edge, which decide what moves at it.

Cycle 4
Steady flow: beat 3 enters while beat 2 leaves. One beat per edge.
Cycle 5
The consumer stops, so beat 3 must stay. But in_ready is still 1, copied from the edge before, and beat 4 comes in.
Cycle 6
Beat 4 sits where beat 3 was. Beat 3 is gone. Only now does in_ready show the stall.
Cycle 9
Beats 1, 2, 4, 5 and 6 came out: six in, five out.

Measured on the lab bench. The consumer stopped for one edge; the stage heard about it one edge later.

A Stage with a Skid RegisterArrows carry beats, except in_ready and out_ready, which carry the ready flags. in_ready is !skid_valid, a flop output.

Normal flow
With the skid empty, a beat goes straight into the main register while the previous beat leaves.
Follow the calls, values and waits
1. data beat 3: producer → main register
The stall
The consumer drops out_ready, so beat 3 stays in the main register. in_ready is still 1, and beat 4 arrives.
Follow the calls, values and waits
1. call out_ready 0: consumer → main register
2. data beat 4: producer → skid register
Ready falls
The skid is full, so in_ready is 0 from the next edge. The producer holds beat 5.
Follow the calls, values and waits
1. call in_ready 0: skid register → producer
Drain
The consumer takes beat 3. At the same edge beat 4 moves from the skid into the main register, so order is kept, and in_ready returns.
Follow the calls, values and waits
1. data beat 3: main register → consumer
2. data beat 4: skid register → main register

Read the diagram as text

producer: offers a beat until it is taken
skid register: skid_valid, skid_data
main register: out_valid, out_data
consumer: drops out_ready to stall

producer → main register: beat, normal flow
producer → skid register: beat during a stall
skid register → main register: drain
main register → consumer: beat out
consumer → main register: out_ready
skid register → producer: in_ready = !skid_valid

The stage holds up to two beats, and no combinational path runs through it from out_ready to in_ready.

Stage style	Beats out of 8	Last beat at cycle	ready path
Registered ready, one register	6 (2 overwritten)	-	from a flop
Accept only when empty	8	18	from a flop
Skid buffer (two registers)	8	13	from a flop

Measured by the run on this question: the consumer stalls one cycle in every four.

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Expected: registered ready: in 8, out 6, mismatched 4 half-rate slice: in 8, out 8, mismatched 0, last beat at cycle 18 skid buffer: in 8, out 8, mismatched 0, last beat at cycle 13 FAIL: registering ready lost 2 of 8 beats

// Three ways to put one register stage on a valid/ready link, fed the same 8 beats
// and drained by the same consumer, which stalls for one cycle every fourth cycle.
module reg_ready (input logic clk, rst_n, in_valid, input logic [7:0] in_data, output logic in_ready,
                  output logic out_valid, output logic [7:0] out_data, input logic out_ready);
  // ready is just the consumer's ready, registered: the stall arrives one edge late
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin in_ready <= 1; out_valid <= 0; end
    else begin
      in_ready <= out_ready;
      if (in_valid && in_ready) begin out_valid <= 1; out_data <= in_data; end   // overwrites!
      else if (out_ready) out_valid <= 0;
    end
endmodule
module half_rate (input logic clk, rst_n, in_valid, input logic [7:0] in_data, output logic in_ready,
                  output logic out_valid, output logic [7:0] out_data, input logic out_ready);
  assign in_ready = !out_valid;            // take a beat only when empty
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) out_valid <= 0;
    else if (in_valid && in_ready) begin out_valid <= 1; out_data <= in_data; end
    else if (out_ready) out_valid <= 0;
endmodule
module skid (input logic clk, rst_n, in_valid, input logic [7:0] in_data, output logic in_ready,
             output logic out_valid, output logic [7:0] out_data, input logic out_ready);
  logic sk_valid; logic [7:0] sk_data;
  assign in_ready = !sk_valid;             // still from a flop: ready while the skid is empty
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin out_valid <= 0; sk_valid <= 0; end
    else if (!out_valid || out_ready) begin             // main register free at this edge
      if (sk_valid) begin out_data <= sk_data; out_valid <= 1; sk_valid <= 0; end
      else begin out_valid <= in_valid; out_data <= in_data; end
    end else if (in_valid && in_ready) begin            // main stalled: catch the beat in the skid
      sk_valid <= 1; sk_data <= in_data;
    end
endmodule
module tb;
  logic clk = 0, rst_n = 0;
  int cyc = 0;
  always #5 clk = ~clk;
  always @(posedge clk) cyc <= cyc + 1;
  wire out_ready = (cyc % 4) != 3;
  for (genvar k = 0; k < 3; k++) begin : lane
    logic in_valid = 0, in_ready, out_valid; logic [7:0] in_data = 0, out_data;
    int sent = 0, got = 0, last = 0, bad = 0;
    if (k == 0) reg_ready dut (.*); else if (k == 1) half_rate dut (.*); else skid dut (.*);
    always @(posedge clk) if (rst_n) begin
      if (in_valid && in_ready) sent <= sent + 1;
      if (out_valid && out_ready) begin
        if (out_data != got + 1) bad <= bad + 1;
        got <= got + 1; last <= cyc;
      end
    end
    // a legal source: hold the beat until it is taken
    always @(posedge clk) if (rst_n) begin
      if (in_valid && in_ready) in_data <= in_data + 1;
      in_valid <= (sent + (in_valid && in_ready) < 8);
      if (!in_valid && sent == 0) in_data <= 1;
    end
  end
  initial begin
    repeat (2) @(posedge clk); #1 rst_n = 1;
    repeat (30) @(posedge clk); #1;
    $display("registered ready: in %0d, out %0d, mismatched %0d", lane[0].sent, lane[0].got, lane[0].bad);
    $display("half-rate slice:  in %0d, out %0d, mismatched %0d, last beat at cycle %0d", lane[1].sent, lane[1].got, lane[1].bad, lane[1].last);
    $display("skid buffer:      in %0d, out %0d, mismatched %0d, last beat at cycle %0d", lane[2].sent, lane[2].got, lane[2].bad, lane[2].last);
    if (lane[0].got != lane[0].sent) $display("FAIL: registering ready lost %0d of %0d beats", lane[0].sent - lane[0].got, lane[0].sent);
    $finish;
  end
endmodule

Self-Check

Tick each key point you covered in your answer.

Key point 1 A registered ready tells the stage about a stall one edge late. Key point 2 So the stage accepts a beat it has nowhere to put, and overwrites one. Key point 3 A slice that accepts only when empty is safe but halves throughput. Key point 4 The fix is a skid buffer: a second register that catches the one beat in flight when the stall arrives. Key point 5 It gives registered ready at full rate, for roughly twice the flops.

What Interviewers Listen For (Mid-Level)

A good mid-level answer explains that a registered ready reports the stall one edge late. It draws the skid buffer with its two registers.

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Misconception

"Registering ready just adds a cycle of latency."

It changes behaviour. The stage takes one beat after the stall begins, with no room for it. The run loses 2 of 8 beats.

Run It

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Edit the code, then run it

// Three ways to put one register stage on a valid/ready link, fed the same 8 beats
// and drained by the same consumer, which stalls for one cycle every fourth cycle.
module reg_ready (input logic clk, rst_n, in_valid, input logic [7:0] in_data, output logic in_ready,
                  output logic out_valid, output logic [7:0] out_data, input logic out_ready);
  // ready is just the consumer's ready, registered: the stall arrives one edge late
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin in_ready <= 1; out_valid <= 0; end
    else begin
      in_ready <= out_ready;
      if (in_valid && in_ready) begin out_valid <= 1; out_data <= in_data; end   // overwrites!
      else if (out_ready) out_valid <= 0;
    end
endmodule
module half_rate (input logic clk, rst_n, in_valid, input logic [7:0] in_data, output logic in_ready,
                  output logic out_valid, output logic [7:0] out_data, input logic out_ready);
  assign in_ready = !out_valid;            // take a beat only when empty
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) out_valid <= 0;
    else if (in_valid && in_ready) begin out_valid <= 1; out_data <= in_data; end
    else if (out_ready) out_valid <= 0;
endmodule
module skid (input logic clk, rst_n, in_valid, input logic [7:0] in_data, output logic in_ready,
             output logic out_valid, output logic [7:0] out_data, input logic out_ready);
  logic sk_valid; logic [7:0] sk_data;
  assign in_ready = !sk_valid;             // still from a flop: ready while the skid is empty
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) begin out_valid <= 0; sk_valid <= 0; end
    else if (!out_valid || out_ready) begin             // main register free at this edge
      if (sk_valid) begin out_data <= sk_data; out_valid <= 1; sk_valid <= 0; end
      else begin out_valid <= in_valid; out_data <= in_data; end
    end else if (in_valid && in_ready) begin            // main stalled: catch the beat in the skid
      sk_valid <= 1; sk_data <= in_data;
    end
endmodule
module tb;
  logic clk = 0, rst_n = 0;
  int cyc = 0;
  always #5 clk = ~clk;
  always @(posedge clk) cyc <= cyc + 1;
  wire out_ready = (cyc % 4) != 3;
  for (genvar k = 0; k < 3; k++) begin : lane
    logic in_valid = 0, in_ready, out_valid; logic [7:0] in_data = 0, out_data;
    int sent = 0, got = 0, last = 0, bad = 0;
    if (k == 0) reg_ready dut (.*); else if (k == 1) half_rate dut (.*); else skid dut (.*);
    always @(posedge clk) if (rst_n) begin
      if (in_valid && in_ready) sent <= sent + 1;
      if (out_valid && out_ready) begin
        if (out_data != got + 1) bad <= bad + 1;
        got <= got + 1; last <= cyc;
      end
    end
    // a legal source: hold the beat until it is taken
    always @(posedge clk) if (rst_n) begin
      if (in_valid && in_ready) in_data <= in_data + 1;
      in_valid <= (sent + (in_valid && in_ready) < 8);
      if (!in_valid && sent == 0) in_data <= 1;
    end
  end
  initial begin
    repeat (2) @(posedge clk); #1 rst_n = 1;
    repeat (30) @(posedge clk); #1;
    $display("registered ready: in %0d, out %0d, mismatched %0d", lane[0].sent, lane[0].got, lane[0].bad);
    $display("half-rate slice:  in %0d, out %0d, mismatched %0d, last beat at cycle %0d", lane[1].sent, lane[1].got, lane[1].bad, lane[1].last);
    $display("skid buffer:      in %0d, out %0d, mismatched %0d, last beat at cycle %0d", lane[2].sent, lane[2].got, lane[2].bad, lane[2].last);
    if (lane[0].got != lane[0].sent) $display("FAIL: registering ready lost %0d of %0d beats", lane[0].sent - lane[0].got, lane[0].sent);
    $finish;
  end
endmodule

Half-Truth

"Use in_ready = !out_valid and you are done."

Safe, but a stage that accepts only when empty moves at most one beat every two cycles. In the run, 8 beats take 18 cycles instead of 13.

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