The Valid/Ready Rules

Where the interviewer goes next. Open a node to practise that follow-up.

What IfProve ItBreak ItCompareScale It

1. The Valid/Ready Rules
2. What IfReady Falling Before ValidL1 Junior

   The sink raised ready, then dropped it two cycles later without any beat arriving. Is that a protocol violation?

   Reveal the Model Answer

   No. ready may rise in advance and fall again before valid is asserted; it carries no hold obligation. The only rule on ready is indirect: if it is high at an edge where valid is high, a beat moved. A checker must report the musts and can warn on the shoulds. It stays silent on freedoms like this one.

   A lit ready with a dark valid is permission with nothing to permit.

   1. Cycle 1

      The controller raises ready: it has room. Nothing is offered.

   2. Cycle 2

      ready drops again. The DMA checker called this a withdrawn offer. But only valid makes an offer, and valid was 0.

   3. Cycle 4

      The real offer from cycle 3 is taken here. The spec: a sink may lower ready before valid rises. Argument over.

   The sink raises ready, drops it with nothing offered, then takes the real offer later. Every step is legal.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 No. Key point 2 ready may rise in advance and fall again before valid is asserted; it carries no hold obligation. Key point 3 The only rule on ready is indirect: if it is high at an edge where valid is high, a beat moved. Key point 4 A checker must report the musts and can warn on the shoulds. Key point 5 It stays silent on freedoms like this one.

   What Interviewers Listen For (Junior)

   A good junior answer says this is legal. It names valid as the only signal that carries a rule to stay high.

   Misconception

   "It's symmetric: whichever signal rises first must hold."

   Only valid must hold. Treating ready the same way rejects legal sinks. One example is a sink that drops ready when its FIFO fills from another port.

   Source AMBA AXI Protocol Specification IHI 0022L §A2.3 Valid-Ready transport

   • Lesson P1.10From the Spec to a Check
   • Problem P1.10.1Properties for the Link
3. Scale ItOne Handshake Checker on Every LinkL2 Mid-LevelL3 Senior

   Your SoC has two hundred valid/ready links. How do you get the handshake rules checked on all of them without editing each block?

   Reveal the Model Answer

   Write one parameterised checker module over clk, rst_n, valid, ready and the payload. Attach it with bind, so every instance gets it without touching the RTL. Make it count antecedent matches (cycles where the rule's trigger held) per link, and report links whose stall rule never started. A silent checker on a link that never stalled checked nothing. The same properties run as assertions in formal.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Write one parameterised checker module over clk, rst_n, valid, ready and the payload. Key point 2 Attach it with bind, so every instance gets it without touching the RTL. Key point 3 Make it count antecedent matches (cycles where the rule's trigger held) per link, and report links whose stall rule never started. Key point 4 A silent checker on a link that never stalled checked nothing. Key point 5 The same properties run as assertions in formal.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer attaches one checker to every link with bind. It gives the checker a parameter for the payload width, so one module fits every link.

   Wrong Altitude

   "Each block owner adds assertions inside their RTL."

   Rules drift between copies, and some links get none. RTL edits for verification also need RTL reviews. A bound checker is written once and reaches every instance.

   • Lesson P1.10From the Spec to a Check
   • Lesson P2.16The AXI Protocol Checker
   • Problem P2.16.1Six Properties for the Link
4. Break ItThe First Valid After ResetL1 JuniorL2 Mid-Level

   Reset is released at edge 10. Can the source drive valid high so that the sink sees it at edge 10?

   Reveal the Model Answer

   No. AXI requires valid to stay low at least until the rising edge after reset goes high. The earliest it may rise is at a rising edge after release. So a sink first sees it one edge later. Reset may be asserted asynchronously, but it is released synchronously. A source that raises valid too early can hand a beat to a sink that is still leaving reset.

   1. Cycle 0

      Reset is asserted. Every VALID is 0; the memory holds its READYs low too.

   2. Cycle 2

      The first edge where ARESETn samples high. Nothing may be driven yet; after this edge the manager is allowed to offer.

   3. Cycle 3

      AWVALID rises after edge 2 and AWREADY is high: the first address moves at edge 3. The checker would report reset for any VALID seen high at edges 0 or 1.

   Measured on the AXI lesson bench. ARESETn is first sampled high at edge 2, so the first address moves at edge 3.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 No. Key point 2 AXI requires valid to stay low at least until the rising edge after reset goes high. Key point 3 The earliest it may rise is at a rising edge after release. Key point 4 So a sink first sees it one edge later. Key point 5 Reset may be asserted asynchronously, but it is released synchronously. Key point 6 A source that raises valid too early can hand a beat to a sink that is still leaving reset.

   What Interviewers Listen For (Junior)

   A good junior answer knows that valid must stay low while reset is active.

   Missed Corner

   "Disable the whole checker while reset is low and you are done."

   disable iff (!rst_n) stops checking during reset, so a valid driven high in reset is never seen. The reset rule needs its own property.

   Source AMBA AXI Protocol Specification IHI 0022L §A2.1.2 Reset

   • Lesson P1.3Handshakes: Request and Acknowledge, Valid and Ready
   • Lesson P2.2The Handshake, the Clock and Reset, AXI Style
   • Problem P2.2.1Catch the Broken Managers
5. Prove ItSolve P2.2.1: Catch the Broken ManagersSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem P2.2.1

6. CompareStrobe, Four-Phase and Valid/ReadyL0 FresherL1 Junior

   How does a valid/ready handshake differ from a plain strobe, and from a four-phase req/ack handshake?

   Reveal the Model Answer

   A strobe is a one-way pulse that assumes the receiver can always take the data. If it cannot, data is lost. A four-phase req/ack handshake needs no shared clock: req rises, ack rises, req falls, ack falls. So it suits clock crossings, but costs four transitions per item. Valid/ready uses the shared clock to do this in one edge per beat, with backpressure (the sink can stall the source).

   1. Cycle 1

      Phase 1: the sender places 7c and raises req.

   2. Cycle 2

      Phase 2: the receiver has the byte and raises ack. This is the transfer.

   3. Cycle 4

      Phase 3: the sender sees ack and drops req.

   4. Cycle 5

      Phase 4: the receiver drops ack. Both wires are back at 0, ready for the next byte.

   The data stays stable from phase 1 until phase 3. So the receiver may take it at any time while req is high.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A strobe is a one-way pulse that assumes the receiver can always take the data. Key point 2 If it cannot, data is lost. Key point 3 A four-phase req/ack handshake needs no shared clock: req rises, ack rises, req falls, ack falls. Key point 4 So it suits clock crossings, but costs four transitions per item. Key point 5 Valid/ready uses the shared clock to do this in one edge per beat, with backpressure (the sink can stall the source).

   What Interviewers Listen For (Fresher)

   A good fresher answer says a strobe gives the receiver no way to say "wait". So the receiver cannot slow the sender down.

   • Lesson P1.3Handshakes: Request and Acknowledge, Valid and Ready
7. What IfBuses Without a Per-Beat ValidL1 JuniorL2 Mid-Level

   APB and AHB have no valid/ready pair per channel. How do they apply backpressure?

   Reveal the Model Answer

   The requester always moves first, and the completer can only stretch the current transfer. APB holds the access phase while PREADY is low. AHB extends the data phase while HREADY is low. There is one flow-control point per transfer, not one per channel. So reads and writes cannot overlap independently, the way AXI channels do.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The requester always moves first, and the completer can only stretch the current transfer. Key point 2 APB holds the access phase while PREADY is low. Key point 3 AHB extends the data phase while HREADY is low. Key point 4 There is one flow-control point per transfer, not one per channel. Key point 5 So reads and writes cannot overlap independently, the way AXI channels do.

   What Interviewers Listen For (Junior)

   A good junior answer names PREADY on APB and HREADY on AHB as the signals that add wait cycles.

   • Lesson P3.3Wait States and PREADY
   • Lesson P4.4Wait States and What May Change
8. Prove ItSolve P1.3.1: Implement a SinkSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem P1.3.1