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Interview Question · Waveform

Drawing a UART Frame

L0 FresherL1 Junioruartframing
  • Likely at Google
  • Likely at Analog Devices

The interviewer asks

The line idles high and runs 8N1. Draw the frame for 0xA5 on the wire and tell me how many bit-times it takes. Then add even parity.

text
8N1, one slot per bit-time; fill in the data bits for A5h.
idle | start | d0 d1 d2 d3 d4 d5 d6 d7 | stop | idle
  1  |   0   |  ?  ?  ?  ?  ?  ?  ?  ? |   1  |  1
Where would an even-parity bit go?
Reveal the Model Answer

Idle is 1. The frame starts with a 0 start bit. Then come the eight data bits, least significant bit first, and a 1 stop bit. For A5h that is 0, then 1 0 1 0 0 1 0 1, then 1: ten bit-times. Even parity adds one bit before the stop bit, chosen so the count of 1s is even. A5h already has four 1s, so the parity bit is 0 and the frame takes eleven bit-times.

0xA5 on a UART
startdata 0data 1data 2data 3data 4data 5data 6data 7stop 012345678910111213141516171819202122232425rxsamplerx sampled at 4.6875rx sampled at 4.8125rx sampled at 4.9375rx sampled at 6.6875rx sampled at 6.8125rx sampled at 6.9375rx sampled at 8.6875rx sampled at 8.8125rx sampled at 8.9375rx sampled at 10.6875rx sampled at 10.8125rx sampled at 10.9375rx sampled at 12.6875rx sampled at 12.8125rx sampled at 12.9375rx sampled at 14.6875rx sampled at 14.8125rx sampled at 14.9375rx sampled at 16.6875rx sampled at 16.8125rx sampled at 16.9375rx sampled at 18.6875rx sampled at 18.8125rx sampled at 18.9375rx sampled at 20.6875rx sampled at 20.8125rx sampled at 20.9375
Read phases and sample points (transmitter half bit)
  • start: columns 2 through 3.
  • data 0: columns 4 through 5.
  • data 1: columns 6 through 7.
  • data 2: columns 8 through 9.
  • data 3: columns 10 through 11.
  • data 4: columns 12 through 13.
  • data 5: columns 14 through 15.
  • data 6: columns 16 through 17.
  • data 7: columns 18 through 19.
  • stop: columns 20 through 21.
  • rx sampled at 4.688, 4.813, 4.938, 6.688, 6.813, 6.938, 8.688, 8.813, 8.938, 10.688, 10.813, 10.938, 12.688, 12.813, 12.938, 14.688, 14.813, 14.938, 16.688, 16.813, 16.938, 18.688, 18.813, 18.938, 20.688, 20.813, 20.938.

Generated and decoded back. A start bit, eight data bits least significant first, and a stop bit: 10 bit-times. Dots mark where a receiver samples.

0xA5 with even parity
startdata 0data 1data 2data 3data 4data 5data 6data 7even paritystop 0123456789101112131415161718192021222324252627rxsamplerx sampled at 4.6875rx sampled at 4.8125rx sampled at 4.9375rx sampled at 6.6875rx sampled at 6.8125rx sampled at 6.9375rx sampled at 8.6875rx sampled at 8.8125rx sampled at 8.9375rx sampled at 10.6875rx sampled at 10.8125rx sampled at 10.9375rx sampled at 12.6875rx sampled at 12.8125rx sampled at 12.9375rx sampled at 14.6875rx sampled at 14.8125rx sampled at 14.9375rx sampled at 16.6875rx sampled at 16.8125rx sampled at 16.9375rx sampled at 18.6875rx sampled at 18.8125rx sampled at 18.9375rx sampled at 20.6875rx sampled at 20.8125rx sampled at 20.9375rx sampled at 22.6875rx sampled at 22.8125rx sampled at 22.9375
Read phases and sample points (transmitter half bit)
  • start: columns 2 through 3.
  • data 0: columns 4 through 5.
  • data 1: columns 6 through 7.
  • data 2: columns 8 through 9.
  • data 3: columns 10 through 11.
  • data 4: columns 12 through 13.
  • data 5: columns 14 through 15.
  • data 6: columns 16 through 17.
  • data 7: columns 18 through 19.
  • even parity: columns 20 through 21.
  • stop: columns 22 through 23.
  • rx sampled at 4.688, 4.813, 4.938, 6.688, 6.813, 6.938, 8.688, 8.813, 8.938, 10.688, 10.813, 10.938, 12.688, 12.813, 12.938, 14.688, 14.813, 14.938, 16.688, 16.813, 16.938, 18.688, 18.813, 18.938, 20.688, 20.813, 20.938, 22.688, 22.813, 22.938.

Generated and decoded back. Even parity: the parity bit after data 7 is 0.

Bit-time012345678910
Fieldstartd0d1d2d3d4d5d6d7paritystop
8E1, A5h01010010101

A5h is 1010 0101; bit 0 goes first. Drop the parity column for 8N1: ten bit-times.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Fresher)

A good fresher answer draws the start bit low, the data least significant bit first, and the stop bit high. It gets ten bit-times for 8N1 and the right bit order for A5h.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItCompare

  1. Drawing a UART Frame
  2. WhyWhy Start and Stop BitsL0 Fresher

    Why does a UART need a start bit and a stop bit at all?

    Reveal the Model Answer

    There is no clock wire, so the receiver needs one moment it agrees on with the transmitter. That moment is the high-to-low edge of the start bit. The receiver times every bit from that edge. The stop bit returns the line high. So the next frame always begins with a fresh falling edge, even when the last data bit was 0.

    One Frame, Left to Right on the WireThe arrows are time order on the line. Parity is optional; the stop time is 1, 1.5 or 2 bit-times.
    One frame, left to right on the wireThe arrows are time order on the line. Parity is optional; the stop time is 1, 1.5 or 2 bit-times. component Idle line at 1 component Start bit one 0 component Data bits 5 to 8, bit 0 first component Parity bit optional: even or odd component Stop time 1, 1.5 or 2 bits of 1 component Idle or next start a falling edge again
    Read the diagram as text
    • Idle: line at 1
    • Start bit: one 0
    • Data bits: 5 to 8, bit 0 first
    • Parity bit: optional: even or odd
    • Stop time: 1, 1.5 or 2 bits of 1
    • Idle or next start: a falling edge again
    • Idle → Start bit
    • Start bit → Data bits
    • Data bits → Parity bit
    • Parity bit → Stop time
    • Stop time → Idle or next start

    A name like 8N1 or 8E1 gives the data bits, the parity and the stop time. N means none, E even and O odd.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Fresher)

    A good fresher answer names the falling edge of the start bit as the timing reference. It says the stop bit makes sure the next frame has that edge.

  3. CompareThe Cost of No Clock WireL0 FresherL1 Junior

    Compare UART with SPI. What does UART give up by not sending a clock?

    Reveal the Model Answer

    SPI sends the clock, so the receiver samples on an edge it is given, and the rate can change freely. A UART receiver must rebuild bit timing from the start edge and its own clock. So both ends must agree closely on the baud rate. Frames also carry start and stop overhead: 8N1 moves 8 data bits in 10 bit-times. The gain is fewer wires and no shared clock across a cable.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Fresher)

    A good fresher answer names the two costs: both ends must agree on the baud rate, and every frame carries extra bits.

  4. What IfWhat Parity MissesL1 Junior

    Asked if they add parity

    Parity is on. Which corruptions does it catch, and which pass silently?

    Reveal the Model Answer

    It catches any odd number of flipped bits in the data and parity bits. It passes any even number. So a burst that flips two adjacent bits passes. Parity also says nothing about a lost or extra frame. Systems that care add a checksum or CRC at the packet level, above the UART.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer says parity catches an odd number of flipped bits but misses an even number. It says a CRC is needed above the UART.

  5. WhyWhy Parity Misses Two Flipped BitsL0 FresherL1 Junior

    Why does parity miss exactly the corruptions that flip an even number of bits?

    Reveal the Model Answer

    Parity stores one fact: whether the count of ones is even or odd. Flipping one bit changes that count by one, so the parity no longer matches. Flipping two bits changes the count by two or by zero, so it still matches. Any even number of flips cancels the same way.

    Self-Check

    Tick each key point you covered in your answer.

    Half-Truth

    "Parity detects any corrupted byte."

    It detects only an odd number of flipped bits. Two flips in one frame pass.

    Source Lesson P6.2 key points

  6. Prove ItSolve P6.2.1: Encode a UART FrameSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P6.2.1

What People Get Wrong

Common wrong answers and why they fail.

Misconception

"The most significant bit goes first, like SPI."

A UART sends bit 0 first. If the transmitter and receiver disagree on order, every byte comes out reversed. The P6.2 bench sent 55h MSB first, and the receiver decoded AAh.

Source ASIC Point lesson P6.2 (measured): 55h sent MSB first decodes as AAh, 33h as CCh

Misconception

"With parity on, any corrupted byte is caught."

Parity detects only an odd number of flipped bits. Two flips leave the count of 1s unchanged. The P6.2 bench sent A5h, and a corrupted A6h still passed even parity.

Source ASIC Point lesson P6.2 (measured): A6h passes even parity when A5h was sent

Half-Truth

"The receiver checks both stop bits of an 8N2 frame."

The receiver checks only the first stop bit. The second is idle time that the transmitter promises. It helps only when frames run back to back.

Learn It, Then Prove It