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Interview Question · Project Defence

Verifying a Bus Interface IP

L3 SeniorL4 Staffverificationaxitest plan
  • Asked at Infineon
  • Likely at Microchip
  • Likely at Cadence

The Question

The interviewer asks

Walk me through your verification plan for a new AXI subordinate, such as a memory-controller front end. How do you decide you are done?

Reveal the Model Answer

I build four layers. A bound protocol checker catches illegal timing at the interface. Monitors feed a reference model and an ID-aware scoreboard, which catch wrong data, lost beats and illegal reordering. Constrained-random and directed stimulus add adversarial backpressure (stall patterns chosen to stress the design) on every channel. Functional coverage tracks attributes, concurrency and stalls. I call it done when no checker fires, coverage is closed with reviewed waivers, and the bug-find rate has flattened.

Four Layers Around a Bus InterfaceArrows show what each part drives or watches. Only the stimulus drives the design; everything else watches the wires.
Four layers around a bus interfaceArrows show what each part drives or watches. Only the stimulus drives the design; everything else watches the wires. component Stimulus Random and directed,hostile backpressure component Bus interface IP The design under test checker Protocol checker Bound on theinterface component Monitor Rebuilds transactionsfrom the wires component Model andscoreboard Keyed by ID component Functionalcoverage Attributes,concurrency, stalls driveswireswirestransactionssamples
  1. Stimulus

    Random and directed traffic, with stalls chosen to stress every channel.

  2. Protocol checker

    Catches illegal timing at the exact edge, even when the data ends up right.

  3. Scoreboard

    Catches wrong data, lost beats and illegal reordering, which legal wires can hide.

  4. Coverage

    Shows which attributes, overlaps and stalls really happened, so a silent checker means something.

Read the diagram as text
  • Stimulus: Random and directed, hostile backpressure
  • Bus interface IP: The design under test
  • Protocol checker: Bound on the interface
  • Monitor: Rebuilds transactions from the wires
  • Model and scoreboard: Keyed by ID
  • Functional coverage: Attributes, concurrency, stalls
  • Stimulus → Bus interface IP: drives
  • Bus interface IP → Protocol checker: wires
  • Bus interface IP → Monitor: wires
  • Monitor → Model and scoreboard: transactions
  • Monitor → Functional coverage: samples

Each layer catches a bug the others miss. Done means no checker fires and coverage is closed.

LayerCatchesTypical escape
Protocol checker (bound SVA)Withdrawn VALID, unstable payload, LAST on the wrong beat, VALID in reset, 4 KB crossingsA rule nobody wrote; rules that never started because no test stalled
Monitor + reference model + scoreboardWrong data or strobes, lost or duplicated beats, same-ID reordering, wrong responseA reference model that shares the DUT's mistake, such as an address formula that overflows
StimulusExercises bursts, sizes, IDs, outstanding depth, errors, reset mid-trafficCorners random traffic almost never hits: top of address space, exact 4 KB edges, long stalls
CoverageShows what was exercised, sampled from the monitorHoles in the coverage model itself

Each layer answers a different question. The third column shows what a review should probe.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Senior)

A good senior answer names all four layers and says which bug each one catches that the others miss. It gives concrete sign-off criteria.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItScale It

  1. Verifying a Bus Interface IP
  2. What IfWhat a Purchased VIP Does Not DoL3 Senior

    Management bought a commercial AXI VIP. Which parts of your plan does it replace, and which does it not?

    Reveal the Model Answer

    It replaces the protocol checker and much of the stimulus and protocol coverage. That holds only once it is configured to match the interface: widths, ID bits, outstanding limits and optional signals. It does not replace the reference model, the scoreboard, or the design-specific legal subset. It also does not replace a review of its own configuration. A misconfigured VIP silently checks a different interface from the one you built.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Senior)

    A good senior answer lists what stays specific to the design. It makes the team review the VIP configuration against the RTL parameters.

    Tool as Truth

    "The VIP reported no errors, so the DUT is compliant."

    That is true only for the rules and configuration it ran with. Tell a VIP the ID width is 4 when the RTL has 6, and it stops checking the top bits.

    Source AMBA AXI Protocol Specification IHI 0022L §A5.1.1 Transaction ID signals (ID_W_WIDTH, ID_R_WIDTH)

  3. Prove ItProving the Bought Checker FiresL3 Senior

    Prove it: how do you show that the VIP's protocol checker actually fires on your configuration?

    Reveal the Model Answer

    Break each rule once, on purpose, with a small fault in a test agent. Check that the VIP reports it, at the right edge. A checker whose antecedents never fired has checked nothing. Keep these fault tests in regression, so an upgrade or a config change that silences a rule shows up.

    Self-Check

    Tick each key point you covered in your answer.

    Tool as Truth

    "The VIP comes from a vendor, so its checks are proven."

    They are proven for some configuration. Yours may switch rules off, so show each rule fires on your setup.

    Source Lesson P2.16 key points

  4. Break ItCorners Random Traffic Never HitsL2 Mid-LevelL3 Senior

    Your random AXI traffic ran a million transactions clean. Name corners it probably never hit, and how you would make sure it does.

    Reveal the Model Answer

    Random traffic misses corners that need one exact value, such as a burst ending exactly at a 4 KB edge. Others are a WRAP in the top address window and the longest burst at the largest size. So are every ID in flight at once, a stall on the last beat, and reset during a burst. Uniform randomness gives each of these about zero probability. Add weighted constraints toward edges, directed tests for the extremes, and coverage bins that name each corner.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer names boundary cases that random traffic almost never hits. It weights the constraints toward them.

  5. Scale ItFrom One Port to an InterconnectL4 Staff

    Now scale it: an interconnect with eight managers and twelve subordinates. What changes in the verification architecture?

    Reveal the Model Answer

    Bind a checker on every port, and replace the per-port scoreboards with one end-to-end scoreboard. It models the address decode and the ordering per manager and ID. It also models the ID bits the interconnect adds on the way in and removes on the way out. Add system checks: no response to the wrong manager, decode errors for address holes, and bounds on fairness and starvation. Formal suits the decoder and ID logic, while simulation covers data integrity and performance.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Staff)

    A good staff answer separates checking each port's rules from checking routing and order end to end. It gives decode and ID logic to formal, because formal is cheaper there.

  6. WhyHow You Know You Are DoneL3 SeniorL4 Staff

    Walk me through the evidence you would show when your manager asks: is this IP ready for tape-out, yes or no?

    Reveal the Model Answer

    I bring a plan-to-evidence table. It maps every spec rule to a property or scoreboard check, each passing in regression with its antecedent (trigger side) covered. Beside it go closed functional coverage with designer-signed waivers, and explained code coverage holes. I add open bugs at zero or deferred in writing, plus the recent bug-find rate. Then comes the honest part: what was not verified, and why the risk is accepted.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Senior)

    A good senior answer brings a table that links each rule to its check, plus coverage, the bug trend and signed waivers.

  7. Prove ItSolve P2.18.1: Catch Every Broken SubordinateSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P2.18.1

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Half-Truth

"We use the vendor VIP, so the protocol is covered."

A VIP checks only the rules it has, under the configuration you gave it. It knows nothing about your data path or your reference model. It also does not know which legal subset your design promises.

Missed Corner

"Random stimulus will reach every corner eventually."

In the twin, 100,000 uniform random start addresses never land in the top 64-byte window. That is where a 32-bit WRAP formula overflows. There it gets 14 of 16 beat addresses wrong.

Run It
RUNIcarus Verilog · in your browser
Edit the code, then run it
Expected: start 00001008: beat 1 naive 0000100c safe 0000100c, 0 of 16 beats differ start ffffffc8: beat 1 naive ffffff8c safe ffffffcc, 14 of 16 beats differ random starts in the upper half: 49887 of 100000 random starts in the top window: 0 of 100000 FAIL: random starts never reached the top window, where the naive wrap is wrong

Half-Truth

"Done is when coverage reaches 100%."

Coverage measures only the model you wrote. You also need a review of that model against the spec, and zero open checker failures. Without them, 100% says nothing about what you forgot to cover.

Learn It, Then Prove It