← Analog & Mixed-Signal Interviews
Interview Question · Concept
The Differential Pair
The Question
The interviewer asks
How does a differential pair work, and why can it never deliver more than its tail current?
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Reveal the Model Answer
Two matched transistors share one tail current, I_SS. Their drain currents always add up to I_SS, and the differential input decides how it splits. A small input splits it almost linearly. Past a few hundred millivolts one side carries all of I_SS, so the pair steers current but cannot create more. For a differential signal the tail is an AC ground, and each half acts as a common-source stage.
- I_D1
- I_D2
- I_D1 + I_D2
- Differential input v_d -300 mVI_D1 = 25.78 nA · I_D2 = 19.69 µA · I_D1 + I_D2 = 19.72 µA
M2's gate is 300 mV above M1's, so M2 carries almost all of the tail current.
- Differential input v_d 0 VI_D1 = 9.778 µA · I_D2 = 9.778 µA · I_D1 + I_D2 = 19.56 µA
Balance: each side carries 9.78 µA, half of the 19.56 µA tail.
- Differential input v_d 120.2 mVI_D1 = 17.63 µA · I_D2 = 1.959 µA · I_D1 + I_D2 = 19.59 µA
At vd = +120.2 mV, M1 carries 90 % of the total and M2 10 %.
- Differential input v_d 300 mVI_D1 = 19.69 µA · I_D2 = 25.78 nA · I_D1 + I_D2 = 19.72 µA
At +300 mV M2 is down to 25.8 nA, because M1 already has all the current there is.
Read the plot as a table
| Differential input v_d | I_D1 | I_D2 | I_D1 + I_D2 |
|---|---|---|---|
| -400 mV | 1.509 nA | 19.79 µA | 19.79 µA |
| -300 mV | 25.78 nA | 19.69 µA | 19.72 µA |
| -200 mV | 349.7 nA | 19.29 µA | 19.64 µA |
| 0 V | 9.778 µA | 9.778 µA | 19.56 µA |
| 120.2 mV | 17.63 µA | 1.959 µA | 19.59 µA |
| 200 mV | 19.29 µA | 349.7 nA | 19.64 µA |
| 300 mV | 19.69 µA | 25.78 nA | 19.72 µA |
| 400 mV | 19.79 µA | 1.509 nA | 19.79 µA |
Measured on a sky130 pair: the input only decides how the tail current splits. The sum stays close to 19.6 µA.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Fresher)
A good fresher answer explains that a fixed tail current is steered between the two sides. It writes the differential gain as g_m times the load.
What Interviewers Listen For (Mid-Level)
A good mid-level answer links the linear input range to g_m/I_D, and checks the common-mode range. It explains why the tail is an AC ground only for differential signals.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItCompare
- The Differential Pair
-
WhyWhy the Tail Is an AC GroundL1 Junior
Why can you treat the tail node as AC ground for a differential input?
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Reveal the Model Answer
A differential input raises one gate and lowers the other by the same amount. One drain current rises as the other falls, so the total through the tail does not change. With no change in tail current, the tail voltage does not move. Each half then sees a source held still, like a common-source stage.
DC sweepDifferential Output and Tail VoltagePair A: differential output above, tail node below. Whole plot- v(d2) − v(d1)
- v(taila)
- Differential input v_d 0 Vv(d2) − v(d1) = -2.211 pV · v(taila) = 454.2 mV
At balance the slope is 8.238 V/V, the differential gain. The tail is flat at 0.454 V.
- Differential input v_d 300 mVv(d2) − v(d1) = 983.3 mV · v(taila) = 540.4 mV
All the current runs through M1 and the output stops at ISS·RD. The tail now follows the higher gate.
Read the plot as a table
Differential input v_d v(d2) − v(d1) v(taila) -400 mV -989.4 mV 581.8 mV -200 mV -947.2 mV 499.9 mV 0 V -2.211 pV 454.2 mV 200 mV 947.2 mV 499.9 mV 300 mV 983.3 mV 540.4 mV 400 mV 989.4 mV 581.8 mV Around balance the tail node stays flat at 0.454 V while the differential output swings.
Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve E5.3.1: A Bench for the Five-Transistor OTASimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
What IfThe Tail Node Under a Common-Mode InputL1 JuniorL2 Mid-Level
What if the input is common-mode instead? Is the tail still an AC ground?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
No. Both gates rise together, so both currents try to rise and the tail current must change. The tail node then moves with the input. The tail's output resistance limits that change, and that is what gives the pair its common-mode rejection.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"The tail node is always an AC ground."
Only for a differential input. A common-mode input changes the tail current, and the tail voltage follows it.
Source Lesson E5.1 key points
-
CompareDifferential Gain vs Common-Mode GainL1 JuniorL2 Mid-Level
Compare differential and common-mode gain, and say how you measure CMRR in simulation.
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Reveal the Model Answer
Differential gain amplifies the difference between the inputs; common-mode gain is what leaks through when both move together. CMRR is their ratio. Drive both inputs together for A_cm and one input for A_d. The lesson's OTA gave 42.71 dB and -12.66 dB, so 55.37 dB. The hand formula assumes the halves match, but a 5T OTA's output and diode node sit at different voltages.
AC analysisDifferential Gain and Three Common-Mode GainsAd of OTA-A, and Acm as built, with an ideal tail, and with the output held at the level of node x. Whole plot- A_d
- A_cm as built
- A_cm, ideal tail
- A_cm, out at V_x
- Frequency 10 HzA_d = 42.71 dB · A_cm as built = -12.66 dB · A_cm, ideal tail = -14.6 dB · A_cm, out at V_x = -28.44 dB
At 10 Hz: Ad = 42.71 dB, Acm = −12.66 dB, so CMRR = 55.37 dB. An ideal tail barely helps (−14.60 dB). Holding the output at Vx does: −28.44 dB.
- Frequency 1 MHzA_d = 28.04 dB · A_cm as built = -27.3 dB · A_cm, ideal tail = -29.27 dB · A_cm, out at V_x = -41.15 dB
At 1 MHz both gains have fallen by the same output pole, so the CMRR is still 55.35 dB.
Read the plot as a table
Frequency A_d A_cm as built A_cm, ideal tail A_cm, out at V_x 1 Hz 42.71 dB -12.66 dB -14.6 dB -28.44 dB 10 Hz 42.71 dB -12.66 dB -14.6 dB -28.44 dB 100 Hz 42.71 dB -12.66 dB -14.6 dB -28.44 dB 1 kHz 42.71 dB -12.66 dB -14.6 dB -28.44 dB 10 kHz 42.7 dB -12.67 dB -14.61 dB -28.44 dB 100 kHz 41.63 dB -13.74 dB -15.68 dB -29.24 dB 1 MHz 28.04 dB -27.3 dB -29.27 dB -41.15 dB 10 MHz 8.185 dB -45.35 dB -49.02 dB -49.62 dB 100 MHz -12.57 dB -47.74 dB -62.52 dB -47.91 dB Measured on ngspice 42 (the lab netlist, 20 points per decade).
Self-Check
Tick each key point you covered in your answer.
-
What IfThe Input Common-Mode RangeL1 JuniorL2 Mid-Level
Asked if they assume any common-mode input works
What if the input common-mode voltage is too low or too high for the pair?
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Reveal the Model Answer
Too low, and the tail device leaves saturation, so the tail current falls. Too high, and an input device leaves saturation. The lesson's OTA ran from 0.811 V to 1.274 V. DC gain and follower error can hide the lower edge, so check the saturation margins and the tail current directly.
DC sweepOpen-Loop Gain and Tail Current Across the Input RangeGain from the two-follower bench (above) and M5's drain current on a log axis (below), with the measured saturation edges. Whole plot- open-loop gain
- tail current
- Input V_CM 300 mVopen-loop gain = 40.34 dB · tail current = 5.149 nA
At 0.3 V the tail carries 5.1 nA, yet the DC gain still reads 40.3 dB and a follower would be only 6.3 mV off. Nothing at DC warns you.
- Input V_CM 810.6 mVopen-loop gain = 42.85 dB · tail current = 17.44 µA
M5 leaves saturation at 0.811 V; the hand estimate was 0.830 V. Below this the tail current falls by decades.
- Input V_CM 900 mVopen-loop gain = 42.73 dB · tail current = 18.67 µA
Mid-range: 42.73 dB and 18.67 µA.
- Input V_CM 1.274 Vopen-loop gain = 41.26 dB · tail current = 19.66 µA
M1 leaves saturation at 1.274 V; the hand estimate was 1.255 V. Body effect has raised Vth1 from 0.637 V to 0.702 V here, because the tail rose with the inputs while M1's body stayed at ground.
- Input V_CM 1.4 Vopen-loop gain = 39.43 dB · tail current = 19.77 µA
Above the edge the gain sags to 39.4 dB and the follower's error grows to 60.9 mV.
Read the plot as a table
Input V_CM open-loop gain tail current 0 V 18.85 dB 4.168 pA 200 mV 38.43 dB 353.3 pA 300 mV 40.34 dB 5.149 nA 400 mV 40.89 dB 69.88 nA 600 mV 42.39 dB 4.478 µA 800 mV 42.86 dB 17.14 µA 810.6 mV 42.85 dB 17.44 µA 900 mV 42.73 dB 18.67 µA 1 V 42.55 dB 19.11 µA 1.2 V 41.89 dB 19.54 µA 1.274 V 41.26 dB 19.66 µA 1.4 V 39.43 dB 19.77 µA 1.6 V 38.7 dB 19.82 µA 1.8 V 38.64 dB 19.82 µA Below 0.811 V the tail current falls by decades, while the DC gain still looks fine. Check the tail current directly.
Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve E5.1.1: Steer the CurrentSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Misconception
"A bigger input step gives a proportionally bigger output current."
Only while the pair is near balance. Once the input passes the linear range, all of I_SS goes to one side and the current stops growing.
Source ASIC Point lesson E5.1 (measured steering)
Half-Truth
"A low g_m/I_D only costs current."
It also widens the linear range. In the lesson 90 % steering took 120 mV at g_m/I_D = 17.6 per volt and 284 mV at 6.7 per volt.
Source ASIC Point lesson E5.1 (measured)