Choosing a State Encoding

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfCompareScale It

1. Choosing a State Encoding
2. WhyWhy One-Hot Decoding Is CheapL1 JuniorL2 Mid-Level

   Why can one-hot be fast, when the full-compare version above was not? Read this version.

   module seq5 (input logic clk, rst_n, start, last, output logic load, run, done);
     localparam int IDLE = 0, LOAD = 1, RUN = 2, DRAIN = 3, DONE = 4;   // bit positions
     (* fsm_encoding = "none" *) logic [4:0] st_q;
     logic [4:0] st_d;
     always_ff @(posedge clk or negedge rst_n)
       if (!rst_n) st_q <= 5'b00001;
       else        st_q <= st_d;
     always_comb begin
       st_d = '0;                        // each arm sets one bit
       unique case (1'b1)                // reverse case: each arm tests one state bit
         st_q[IDLE]:  if (start) st_d[LOAD] = 1'b1; else st_d[IDLE] = 1'b1;
         st_q[LOAD]:  st_d[RUN] = 1'b1;
         st_q[RUN]:   if (last) st_d[DRAIN] = 1'b1; else st_d[RUN] = 1'b1;
         st_q[DRAIN]: st_d[DONE] = 1'b1;
         st_q[DONE]:  st_d[IDLE] = 1'b1;
         default:     st_d[IDLE] = 1'b1;
       endcase
     end
     assign load = st_q[LOAD];
     assign run  = st_q[RUN];
     assign done = st_q[DONE];
   endmodule
   module tb;
     logic clk = 0, rst_n = 1, start = 0, last = 0, load, run, done;
     seq5 dut (.*);
     always #5 clk = ~clk;
     initial begin
       #1 rst_n = 0; #1 rst_n = 1;
       start = 1; @(posedge clk); #1 start = 0;
       @(posedge clk); #1 $display("two edges after start: load=%b run=%b", load, run);
       last = 1; @(posedge clk); #1 last = 0;
       @(posedge clk); #1 $display("two edges after last: done=%b", done);
       $finish;
     end
   endmodule
   

   Reveal the Model Answer

   Each arm tests one state bit, not the whole 5-bit vector. So "am I in RUN?" is one wire, and each next-state bit is a small OR of a few terms. On this flow it is 13 cells and 3 levels, against 27 and 5 for full-vector compares. The coding has to use the one-hot property for the encoding to save logic.

   RUNIcarus Verilog · in your browser

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: two edges after start: load=0 run=1 two edges after last: done=1

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Each arm tests one state bit, not the whole 5-bit vector. Key point 2 So "am I in RUN?" Key point 3 is one wire, and each next-state bit is a small OR of a few terms. Key point 4 On this flow it is 13 cells and 3 levels, against 27 and 5 for full-vector compares. Key point 5 The coding has to use the one-hot property for the encoding to save logic.

   Misconception

   "Writing enum values as one-hot is enough to get one-hot logic."

   A case on the whole vector still compares all bits, as the full-compare version shows. Testing single bits is what makes it cheap.

   Source Measured: this run and the root twin, Yosys 0.70+290 (OSS CAD Suite 2026-11-02), slang front end, synth -flatten with ABC, ltp -noff

   • Lesson R3.2Coding an FSM: States, Encodings, the Default
3. What IfWhen the Synthesizer Re-Encodes Your FSML2 Mid-LevelL3 Senior

   What if the tool does not keep your encoding? How would you notice, and when does it matter?

   Reveal the Model Answer

   Look at the flop count and the FSM section of the synthesis log. Here the binary machine came out with 5 flops: Yosys re-encoded it one-hot. That is often fine for speed. It matters when other logic reads the state code or the code crosses a clock domain. It also matters when recovery logic depends on it.

   module seq5 (input logic clk, rst_n, start, last, output logic load, run, done);
     typedef enum logic [2:0] {IDLE, LOAD, RUN, DRAIN, DONE} state_e;   // binary 0 to 4
     state_e st_q;
     state_e st_d;
     always_ff @(posedge clk or negedge rst_n)
       if (!rst_n) st_q <= IDLE;
       else        st_q <= st_d;
     always_comb begin
       st_d = st_q;                      // stay, unless an arm moves
       case (st_q)
         IDLE:  if (start) st_d = LOAD;
         LOAD:  st_d = RUN;
         RUN:   if (last) st_d = DRAIN;
         DRAIN: st_d = DONE;
         DONE:  st_d = IDLE;
         default: st_d = IDLE;         // any unnamed code: back to IDLE
       endcase
     end
     assign load = (st_q == LOAD);
     assign run  = (st_q == RUN);
     assign done = (st_q == DONE);
   endmodule
   

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Look at the flop count and the FSM section of the synthesis log. Key point 2 Here the binary machine came out with 5 flops: Yosys re-encoded it one-hot. Key point 3 That is often fine for speed. Key point 4 It matters when other logic reads the state code or the code crosses a clock domain. Key point 5 It also matters when recovery logic depends on it.

   Missed Corner

   "Re-encoding cannot change behaviour."

   It keeps behaviour only for the reachable states. Codes the machine never reaches from reset, and the arms for them, can disappear.

   Source Yosys 0.70+290 command help, help fsm_recode and help fsm_detect; lesson R3.2 measured netlists

   • Lesson R3.2Coding an FSM: States, Encodings, the Default
4. What IfA State Code That Crosses a Clock DomainL3 Senior

   What if the state register is read in another clock domain, and the tool re-encodes it?

   Reveal the Model Answer

   Then the reader may see a code that changes several bits at once, so it can sample a mix of two states. First, do not cross the state register at all. Cross a one-bit status through a synchronizer, or use a handshake. If you must keep the code, tell the tool not to re-encode it, and check the log after every run.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Then the reader may see a code that changes several bits at once, so it can sample a mix of two states. Key point 2 First, do not cross the state register at all. Key point 3 Cross a one-bit status through a synchronizer, or use a handshake. Key point 4 If you must keep the code, tell the tool not to re-encode it, and check the log after every run.

   Missed Corner

   "Gray-code the states and the crossing is safe."

   Only if every transition changes one bit and the tool keeps the code. A branching or re-encoded machine can change several bits at once.

   Source Mehta, ASIC/SoC Functional Design Verification (2018) ch. 8.3.4 Multi-bit synchronization

   • Lesson R3.2Coding an FSM: States, Encodings, the Default
   • Lesson R6.4Gray Codes and the Asynchronous FIFO
5. CompareGray-Coded States vs One-HotL2 Mid-Level

   Compare a Gray-coded state register with one-hot. When would you pick Gray?

   Reveal the Model Answer

   Pick Gray when the machine walks a fixed loop, like a counter, and you want one bit to change per step. Each step then toggles one flop instead of two. It also matters if the state is read in another clock domain, because a Gray step is never a torn value. One-hot is usually better for speed in a branching machine.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Pick Gray when the machine walks a fixed loop, like a counter, and you want one bit to change per step. Key point 2 Each step then toggles one flop instead of two. Key point 3 It also matters if the state is read in another clock domain, because a Gray step is never a torn value. Key point 4 One-hot is usually better for speed in a branching machine.

   Misconception

   "You can safely synchronize a binary state register into another domain."

   Several bits can change in one step. The receiver can then catch a mix of old and new bits, which is a state that never existed.

   Source Mehta, ASIC/SoC Functional Design Verification (2018) ch. 8.3.4 Multi-bit synchronization

   • Lesson R6.2The Two-Flop Synchronizer and What It Cannot Carry
   • Lesson R3.2Coding an FSM: States, Encodings, the Default
6. Scale ItSplitting a Very Large FSML3 Senior

   Scale it up: a protocol controller has grown to 60 states and misses timing. What do you do?

   Reveal the Model Answer

   First look for hidden counters: chains of states that only count cycles. Replace them with one counter and one waiting state. Then split the rest into a main machine and small sub-machines that talk through start and done signals. Each piece gets fewer states, smaller next-state logic, and its own tests.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 First look for hidden counters: chains of states that only count cycles. Key point 2 Replace them with one counter and one waiting state. Key point 3 Then split the rest into a main machine and small sub-machines that talk through start and done signals. Key point 4 Each piece gets fewer states, smaller next-state logic, and its own tests.

   What Interviewers Listen For (Senior)

   A good senior answer looks for structure before it tunes encodings. It keeps each split machine testable on its own.

   Wrong Altitude

   "Try one-hot, then binary, and keep whichever passes."

   Encoding tweaks shave a level or two. A 60-state machine usually hides a counter or two machines, and fixing that removes the problem.

   • Lesson R3.2Coding an FSM: States, Encodings, the Default
   • Lesson R3.5A Protocol Controller: The APB Completer