Why Synthesis Builds a Latch

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WhyWhat IfProve ItBreak ItCompareScale It

1. Why Synthesis Builds a Latch
2. WhyWhy an Unwanted Latch Is a ProblemL1 JuniorL2 Mid-Level

   Why is an unintended latch a real problem and not just a lint warning?

   Reveal the Model Answer

   The latch is memory the spec never asked for, so the output can show a stale value. While its enable is active the latch is transparent, so glitches on its input pass straight through. Static timing and test tools treat latches specially, so many teams avoid them to keep those steps simple. The design may work in RTL simulation and still fail in the lab.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The latch is memory the spec never asked for, so the output can show a stale value. Key point 2 While its enable is active the latch is transparent, so glitches on its input pass straight through. Key point 3 Static timing and test tools treat latches specially, so many teams avoid them to keep those steps simple. Key point 4 The design may work in RTL simulation and still fail in the lab.

   Missed Corner

   "It passed the tests, so the latch is harmless."

   Tests pass when they never take the unassigned path. In lesson R1.3 the bench never dropped the enable, so the stale output was never seen.

   Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 9.2 Unintentional latch inference

   • Lesson R1.3always_comb and the Latch Nobody Asked For
3. CompareA Latch Next to a Flip-FlopL1 JuniorL2 Mid-Level

   Compare a latch and a flip-flop fed the same data. What does this print?

   module tb;
     logic clk = 0, d = 0, q_latch, q_flop;
     always_latch if (clk) q_latch = d;          // transparent while clk is high
     always_ff @(posedge clk) q_flop <= d;       // samples only at the rising edge
     always #10 clk = ~clk;                      // rising edges at 10, 30
     initial begin
       #12 d = 1;                                // d rises while clk is high
       #1 $display("t=13 (clk high): latch=%b flop=%b", q_latch, q_flop);
       #4 d = 0;
       #1 $display("t=18 (clk high): latch=%b flop=%b", q_latch, q_flop);
       #4 d = 1;                                 // t=22: clk is low now
       #1 $display("t=23 (clk low):  latch=%b flop=%b", q_latch, q_flop);
       #8 $display("t=31 (after edge): latch=%b flop=%b", q_latch, q_flop);
       $finish;
     end
   endmodule
   

   Reveal the Model Answer

   The latch follows d while the clock is high, so it shows 1 at t=13 and 0 at t=18. The flop changes only at rising edges. It took 0 at t=10 and holds it until t=30, when it takes 1. When the clock is low, the latch holds. Designers use latches on purpose in clock gating cells and in some latch-based pipelines.

   RUNIcarus Verilog · in your browser

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: t=13 (clk high): latch=1 flop=0 t=18 (clk high): latch=0 flop=0 t=23 (clk low): latch=0 flop=0 t=31 (after edge): latch=1 flop=1

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The latch follows d while the clock is high, so it shows 1 at t=13 and 0 at t=18. Key point 2 The flop changes only at rising edges. Key point 3 It took 0 at t=10 and holds it until t=30, when it takes 1. Key point 4 When the clock is low, the latch holds. Key point 5 Designers use latches on purpose in clock gating cells and in some latch-based pipelines.

   Misconception

   "A latch is a flop that triggers on a level."

   A flop samples once per edge. A latch passes its input through for the whole active level, so several changes in one phase all reach the output.

   Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 9.1 Modeling latches

   • Lesson R1.3always_comb and the Latch Nobody Asked For
   • Lesson R2.3Enables and Gated Clocks
4. What IfAlways_comb and a Missing AssignmentL1 JuniorL2 Mid-Level

   Asked if they say always_comb prevents latches

   What if the decoder is written with always_comb instead of always @*? Is the latch gone?

   Reveal the Model Answer

   No. Simulation behaves the same, and the output still holds its value when en is low. The difference is in the tools that read the intent. Lint names the latch, and many synthesizers warn or stop. On this site's flow, synthesis refuses the block with a logic-loop error. Either way, you still have to add the missing assignment yourself.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 No. Key point 2 Simulation behaves the same, and the output still holds its value when en is low. Key point 3 The difference is in the tools that read the intent. Key point 4 Lint names the latch, and many synthesizers warn or stop. Key point 5 On this site's flow, synthesis refuses the block with a logic-loop error. Key point 6 Either way, you still have to add the missing assignment yourself.

   Misconception

   "always_comb and always @* simulate differently here."

   For this code both wake on any input change and both hold y when nothing assigns it. The difference shows only in lint and synthesis.

   Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 7.2 The always and always_comb procedures

   Tool as Truth

   "Our synthesizer accepted it, so it is not a latch."

   Tools differ: some build the latch and only warn. The report, not a clean exit, tells you what was built.

   Source Lesson R1.3 claims: the plain Yosys front end stops with "Latch inferred"; the slang front end reports a logic loop

   • Lesson R1.3always_comb and the Latch Nobody Asked For
5. Break ItWhen a Default Assignment Hides a BugL2 Mid-Level

   How can the "assign a default at the top" fix itself hide a functional bug?

   Reveal the Model Answer

   The default removes the latch, but it also gives a value to any arm you forgot. A missing arm then outputs the default quietly, often zero, and no tool complains. Choose a default that the spec allows, and make the testbench cover every input value. Some teams use unique case, so that simulation reports a value no arm matches.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The default removes the latch, but it also gives a value to any arm you forgot. Key point 2 A missing arm then outputs the default quietly, often zero, and no tool complains. Key point 3 Choose a default that the spec allows, and make the testbench cover every input value. Key point 4 Some teams use unique case, so that simulation reports a value no arm matches.

   Half-Truth

   "No latch in the report means the decode is complete."

   The report only says every path assigns something. It cannot say the value on each path is the right one.

   • Lesson R1.3always_comb and the Latch Nobody Asked For
   • Lesson R1.5Case Statements: Priority, Parallel, Unique
6. Scale ItA Team Rule for Latch-Free Combinational CodeL3 Senior

   You lead an RTL team. What rules and checks keep unintended latches out of every block?

   Reveal the Model Answer

   Make always_comb mandatory for combinational blocks and always_latch for the rare intended latch. Run lint on every commit, with a latch inference message as an error. Make the synthesis latch count a gate in the flow, with a reviewed waiver list for intended latches. Review default values against the spec, because removing a latch can hide a missing case.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Make always_comb mandatory for combinational blocks and always_latch for the rare intended latch. Key point 2 Run lint on every commit, with a latch inference message as an error. Key point 3 Make the synthesis latch count a gate in the flow, with a reviewed waiver list for intended latches. Key point 4 Review default values against the spec, because removing a latch can hide a missing case.

   What Interviewers Listen For (Senior)

   A good senior answer turns the coding rule into automatic gates: lint severity, a latch-count check in synthesis, and a waiver review. It names who owns each gate.

   Wrong Altitude

   "We tell people to be careful with if statements."

   Advice does not scale. A senior answer puts the check in the flow, so a latch fails the build before review.

   • Lesson R7.3Coding for Review and Debug
   • Lesson R1.3always_comb and the Latch Nobody Asked For
7. Prove ItSolve R1.3.1: The Decoder That RememberedSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem R1.3.1