Interview Question · Code Reading
A Gate That Feeds Itself
The Question
The interviewer asks
What does this circuit do when en is 0, and when en is 1?
module ring (input logic en, output logic y);
assign y = ~(y & en);
endmoduleYou have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
With en at 0, y is simply 1. With en at 1, y = ~y, which has no stable value. Real gates oscillate at a rate set by their delay, like a ring oscillator. A zero-delay simulator keeps re-evaluating in the same time step, so it hangs or hits an iteration limit. The synthesis check reports a combinational loop.
The run on this question, one column per ns from 8 to 15 ns. After en rises at 10 ns, y flips every 1 ns: 9 toggles in 10 ns.
The same gate with a 1 ns delay added, so the oscillation becomes visible.
en=0: y=1, 0 toggles en=1: 9 toggles in 10 nsSelf-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Fresher)
A good fresher answer tries both values of en. For en = 1 it says there is no stable value and calls it a combinational loop.
What Interviewers Listen For (Mid-Level)
A good mid-level answer separates three views. Real gates oscillate, a zero-delay simulation hangs, and lint and the synthesis check flag the loop. It breaks the loop with a flop.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItCompare
- A Gate That Feeds Itself
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WhyWhy Timing Analysis Cannot Time a LoopL1 JuniorL2 Mid-Level
Why can't static timing analysis handle a combinational loop?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
STA adds delays along paths from a start point, such as a flop or an input, to an end point. Around a loop, a path comes back to where it started, so the arrival time has no limit. STA tools report loops for that reason. A tool that cuts a loop to continue may hide a real path.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"STA just adds up the loop delay once."
Adding it once is an arbitrary cut. Where the tool cuts changes which paths it reports, so the result is not a real timing check.
Source OpenSTA 3.1.0 check_setup -loops (as listed in lesson L2.5)
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Break ItA Loop That Is Never ActiveL2 Mid-LevelL3 Senior
Break it: the loop passes through two muxes whose selects are never set to close it at the same time. Is that safe?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Functionally it may never cycle. But the structural checks and STA see wires, not select values, so they still report a loop. Every team must then waive it and re-check it after each change. Recode it so no structural loop exists, for example by sharing one mux.
Self-Check
Tick each key point you covered in your answer.
Misconception
"It is a false loop, so tools ignore it."
The checks work on structure. Proving that the selects never close the loop is the designer's job, and every later edit can break it.
Source Yosys 0.70+290 command help,
help check: the check pass finds combinatorial loops, conflicting drivers and undriven wires (as read for lesson R3.3) -
CompareA Combinational Loop vs a LatchL1 JuniorL2 Mid-Level
Compare an accidental combinational loop with a latch. A latch is also feedback, isn't it?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
A latch is feedback with two stable states and a defined way to open and close it. In silicon it is one library cell, so timing tools know its checks. An accidental loop is built from ordinary gates. Its feedback may have no stable state, or two that nothing controls. Write a latch on purpose with
always_latchso tools map it to a latch cell.Self-Check
Tick each key point you covered in your answer.
Half-Truth
"Two cross-coupled gates are the same as a latch cell."
They store a bit, but no tool times them as a latch. The cell has setup and hold checks; the loose gates have none.
Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 9.1 Modeling Latches
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What IfA Loop That Runs Through Two ModulesL2 Mid-Level
Asked if they say lint on each module would catch it
What if each module is clean on its own, and the loop appears only when they are connected?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
That is the common case. Each module has a legal input-to-output path, and the two paths close a loop at the top. Per-module lint cannot see it. Run lint and the synthesis check on the connected design. Lesson R3.3 measured both tools finding such a loop through two modules.
Self-Check
Tick each key point you covered in your answer.
Tool as Truth
"Each block passed lint, so the subsystem has no loops."
A loop is a property of the connection, not of one block. It appears only when both paths are joined.
Source Lesson R3.3, measured on Yosys 0.70+290 (slang front end, synth -flatten, check): "found logic loop in module link" through both modules, and the service refuses the design
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Prove ItSolve R3.3.1: The Link That Moved NothingSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Prove ItSolve R3.3.1: The Link That Moved NothingSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Tool as Truth
"If there were a loop, simulation would hang or show X, so passing tests prove there is none."
A loop with a stable point simulates fine. Two cross-coupled NORs store a bit, and the twin runs with no warning at all.
Run It
Two NOR gates feeding each other, set and then released.
s=0 r=0: q=1 qn=0 FAIL: simulation ran with no warning; the loop silently became a memory bitMisconception
"The output settles to 0 or 1 after a while."
With en at 1 there is no value that satisfies y = ~y. The delayed run toggles every nanosecond for as long as it runs.
Source Measured: the run on design.loop.combinational-loop, Icarus Verilog 12
Buzzword Without Mechanism
Says "it is a latch" and stops.
This loop has no stable state when enabled, so it cannot store anything. A latch is a loop with two stable states and a defined way to set them.