Interview Question · Concept
An Enable vs a Gated Clock
- Likely at Apple
- Likely at Samsung
- Likely at Marvell
The Question
The interviewer asks
A register should keep its value most of the time. Do you add an enable or gate its clock? What is the difference?
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Reveal the Model Answer
An enable keeps the clock running. When en is low, an enabled flop or a feedback mux keeps the old value. The output holds, but every clock edge still reaches the flops. A gated clock stops the edges themselves, so the clock pins and that branch of the clock tree stop switching. Gating saves more power but needs an ICG cell and more care in timing.
- Enable
When
enis 0, the mux feedsqback to D. The value holds, but the clock pin still switches every cycle. - Gate
When
enis 0, the ICG cell stops the clock. The flop holds because it sees no edge, so its clock pin stops switching too.
Read the diagram as text
- d and en: data and enable
- clk: from the clock tree
- Feedback mux: takes d only when en is 1
- Enabled flop: clock pin toggles every cycle
- ICG cell: passes clk only when en is 1
- Gated flop: no clock edges while en is 0
- d and en → Feedback mux: d, en
- Feedback mux → Enabled flop: D
- clk → Enabled flop: every edge
- d and en → ICG cell: en
- clk → ICG cell
- ICG cell → Gated flop: gated clock
Both rows hold the value when en is 0. Only the gated row saves the clock power.
The enabled register holds 5a for ten idle cycles. The synthesizer builds eight enabled flops.
q=5a after 10 idle cycles; 10 clock edges reached the flopsSelf-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Fresher)
A good fresher answer writes if (en) q <= d; and says the clock still toggles. It says gating stops the clock for a whole group of flops.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains why clock power matters: the clock toggles every cycle into a large load. It picks gating only for wide groups that are often idle.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItCompare
- An Enable vs a Gated Clock
-
WhyWhy the Clock Network Burns PowerL0 FresherL1 Junior
Why is the clock network such a large part of dynamic power?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Dynamic power grows with how often a node switches, its capacitance, the square of the supply and the frequency. The clock switches twice every cycle, more than any data signal. It also drives every flop's clock pin and a large buffered tree. So stopping it where it is not needed saves a lot.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"Idle logic burns no power."
Logic whose inputs stop switching saves dynamic power, but the clock into it keeps switching. Leakage also continues while the power is on.
Source Mehta, ASIC/SoC Functional Design Verification (2018) ch. 9.1 Power requirements (dynamic and static power)
-
CompareLetting Synthesis Insert Clock GatesL1 JuniorL2 Mid-Level
Compare writing clock gates by hand with letting synthesis turn your enables into gates.
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Reveal the Model Answer
If the RTL uses plain enables, a synthesis gating step can group flops that share an enable behind one library ICG. The RTL stays simple and simulates like any enabled register. Hand-placed gates give control, for example to gate a whole block from one signal, but must use the library cell.
Self-Check
Tick each key point you covered in your answer.
Misconception
"You must write clock gates in RTL to get any gating."
Plain enables are the input a gating step needs. The Yosys clockgate pass, for example, groups enabled flops behind a library ICG.
Source Yosys 0.70 command reference, help clockgate (as read for lesson R2.3)
-
What IfWhen the Enable Arrives LateL1 JuniorL2 Mid-Level
What if the enable is computed by deep logic and arrives late in the cycle?
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Reveal the Model Answer
With an enable flop,
enis one more input to the D path, so it must meet the flop's setup time. With an ICG,enmust meet the gate's own setup check before the clock rises. That check can be tighter, because the gate sits early in the clock tree. A late enable can stop you from gating.Self-Check
Tick each key point you covered in your answer.
Misconception
"The enable of a clock gate is not a timing path."
The library cell has setup and hold checks on its enable pin, and STA times them like any other path.
Source SkyWater sky130_fd_sc_hd Liberty, cells dlclkp_1 and sdlclkp_1 (as read for lesson L5.6)
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Prove ItSolve R2.3.1: The Accumulator That Added TwiceSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"An enable stops the flop's clock, so it saves the same power as gating."
An enable only chooses what the flop captures. The twin counts ten clock edges at the flops during ten idle cycles.
Run It
The enabled register, with the edges at its clock pin counted while en is 0.
q=5a after 10 idle cycles; 10 clock edges reached the flops FAIL: the enable held q, but every clock edge still reached the flopsSee the Fix
module hold_gated (input logic clk, en, input logic [7:0] d, output logic [7:0] q, output logic gclk);
logic en_l;
always_latch if (!clk) en_l = en; // ICG model: latch plus AND
assign gclk = clk & en_l;
always_ff @(posedge gclk) q <= d; // no enable: the clock itself stops
endmodule
module tb;
logic clk = 0, en = 0, ck_pin;
logic [7:0] d = 8'h00, q;
int edges_idle = 0;
always #5 clk = ~clk;
hold_gated u (.clk(clk), .en(en), .d(d), .q(q), .gclk(ck_pin));
always @(posedge ck_pin) if (!en) edges_idle++;
initial begin
@(negedge clk) begin en = 1; d = 8'h5a; end
@(negedge clk) begin en = 0; d = 8'h00; end
edges_idle = 0;
repeat (10) @(negedge clk) d = d + 8'd1; // ten idle cycles, d keeps changing
$display("q=%h after 10 idle cycles; %0d clock edges reached the flops", q, edges_idle);
if (q == 8'h5a && edges_idle == 0) $display("PASS: the gated clock held q with no clock edges at the flops");
$finish;
end
endmodule
Prints: q=5a after 10 idle cycles; 0 clock edges reached the flops PASS: the gated clock held q with no clock edges at the flops
Missed Corner
Gates the clock with always_ff @(posedge (clk & en)).
That is an AND gate on the clock written in RTL, with the glitch an ICG prevents. Use an enable, or the library cell.
Source Lesson R2.3, measured on its lab bench (Icarus Verilog 12): the AND-gated log wrote one entry twice; the enabled and latch-and-AND versions did not