Interview Question · Waveform
Clock Skew: Help or Harm
- Asked at Qualcomm
The Question
The interviewer asks
The capture clock arrives 300 ps after the launch clock. Look at the timeline. Does this skew help or hurt?
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Reveal the Model Answer
It helps setup and hurts hold on the same capture flop. The late capture edge gives the long path 300 ps more time. But new data from the short path now has 300 ps longer to race in before the delayed edge. The run shows it: the long path is fixed, and the short path now changes inside the hold window.
Clock-to-Q is 300 ps. The short path changes at 350 ps, just after the late capture edge at 300 ps, inside its 100 ps hold window. The long path changes at 900 ps, 400 ps before the capture edge at 1300 ps.
- setup slack
- hold slack
- Capture-clock buffers 0setup slack = 606.7 ps · hold slack = 333.4 ps
No skew: setup slack 0.6067 ns, hold slack 0.3334 ns. The flop's own clock-to-Q protects hold.
- Capture-clock buffers 4setup slack = 900 ps · hold slack = 33.5 ps
4 buffers: hold slack 0.0335 ns, still met.
- Capture-clock buffers 5setup slack = 973.4 ps · hold slack = -39.9 ps
5 buffers: hold slack -0.0399 ns. Setup has grown to 0.9734 ns, and a slower clock would add only to that.
Read the plot as a table
| Capture-clock buffers | setup slack | hold slack |
|---|---|---|
| 0 | 606.7 ps | 333.4 ps |
| 1 | 679.8 ps | 253.8 ps |
| 2 | 753.3 ps | 180.2 ps |
| 3 | 826.6 ps | 106.9 ps |
| 4 | 900 ps | 33.5 ps |
| 5 | 973.4 ps | -39.9 ps |
| 6 | 1.047 ns | -113.3 ps |
| 7 | 1.12 ns | -186.6 ps |
OpenSTA 3.1.0, dfxtp_1 and clkbuf_1 from the sky130_fd_sc_hd tt library, no wires.
A 600 ps path and a 50 ps path, with the capture clock late by 0 or 300 ps.
long path, skew 0: window=39 late=0 long path, skew 300: window=0 late=0 short path, skew 0: window=0 early=0 short path, skew 300: window=40 early=0Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says a late capture clock helps setup and hurts hold. It points to which path each claim is about.
What Interviewers Listen For (Mid-Level)
A good mid-level answer computes the skew budget from both checks before answering. It also mentions that skew around a loop of registers adds up to zero.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfBreak ItCompare
- Clock Skew: Help or Harm
-
CompareUseful Skew Versus a Pipeline RegisterL2 Mid-LevelL3 Senior
Compare fixing a slow stage with useful skew and fixing it with a new pipeline register.
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Reveal the Model Answer
Useful skew borrows time from the next stage, so it needs slack there and costs no latency. A pipeline register adds a whole cycle of time but changes the cycle count, so the RTL and its verification change. Skew is a physical-design fix; a register is an architectural one.
Self-Check
Tick each key point you covered in your answer.
Misconception
"Useful skew adds time to the path at no cost."
The time comes from the neighbouring stage. If that stage has no slack, the violation just moves there.
Source Lesson L5.4 review claims (useful skew trades setup time between adjacent stages)
-
WhyWhy Skew Cannot Fix a LoopL3 Senior
Why can skew not speed up an accumulator, where the register feeds back into itself through an adder?
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Reveal the Model Answer
Around any loop of registers, the skews add up to zero. The time one stage gains, another stage in the loop loses. So the period is bounded below by the average stage delay around the loop. A single-register loop has zero skew to itself, so only faster logic helps.
The MAC's Registers and Its One LoopArrows are data. accfeeds the adder that feedsacc.Illustrative sequence- A path that skew can help
p→ adder →acc: delayingaccgives it time, taken from paths that start atacc. - A common vector latency cancels
accis a vector. This path crosses different bits; giving every bit the same latency moves both ends equally.
Read the diagram as text
- ra, rb: operand registers
- multiplier: stage into p
- p: product register
- adder: acc + p
- acc: accumulator
- ra, rb → multiplier: data
- multiplier → p: data
- p → adder: data
- adder → acc: sum
- acc → adder: acc
R4.5's MAC, mapped to sky130 cells.
Self-Check
Tick each key point you covered in your answer.
Misconception
"Delay the accumulator clock and it gets more time."
The accumulator launches and captures on the same clock pin. Delaying it moves both edges together, so the path gains nothing.
Source Kahng, Lienig, Markov and Hu, VLSI Physical Design: From Graph Partitioning to Timing Closure, ch. 8 (timing closure), as cited in lesson L2.9
- A path that skew can help
-
What IfNegative SkewL2 Mid-Level
Asked if they only discuss positive skew
What if the capture clock arrives earlier than the launch clock instead?
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Reveal the Model Answer
Then the signs flip. The long path loses that much time for setup, and the hold check becomes easier by the same amount. It often happens when data flows against the direction the clock tree was built in.
Self-Check
Tick each key point you covered in your answer.
Misconception
"Negative skew helps both checks because the edge comes sooner."
An early capture edge shortens the time for setup. Only hold benefits.
Source UC Berkeley EECS 151/251A, lecture on sequential timing (setup and hold constraints with skew), as cited in lesson L2.4
-
Break ItHold Failures That Appear After Clock Tree SynthesisL2 Mid-Level
Timing was clean before clock tree synthesis. After it, hundreds of hold violations appear. What happened?
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Reveal the Model Answer
Before CTS the clock is ideal, with the same arrival at every flop. The real tree has buffers, so some capture flops get their clock later than their launch flops. Short paths into those flops now fail hold. That is why hold repair runs after CTS, with propagated clocks.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"The clock tree tool made a mistake; rebuild the tree with zero skew."
Real trees always leave some skew between branches. Hold repair with delay cells on the short paths is the normal step, not a sign of a bad tree.
Source Lesson L5.5 review claims: hold is repaired after CTS with propagated clocks (UC Berkeley EECS 151/251A lecture on sequential timing)
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"Positive skew is free setup margin, so use plenty of it."
The same flop ends other paths. Their hold check loses exactly what setup gains. The twin uses 400 ps and the short path catches the next value.
Run It
400 ps of capture skew on a flop that ends a 600 ps path and a 50 ps path.
skew 400: long path window=0 late=0 skew 400: short path window=40 early=40 FAIL: the skew that fixed setup on the long path broke hold on the short pathSee the Fix
`timescale 1ps/1ps
// One timing path, simulated with real delays (ps). A 4-bit counter launches a new value at
// every edge. The logic delays it by DLY. A capture flop with setup TSU and hold TH samples it
// on a clock that arrives SKEW ps late. Each capture is compared with the value it should get.
module path #(parameter int PERIOD = 1000, DLY = 50, SKEW = 0, TCQ = 300, TSU = 200, TH = 100) ();
logic clk = 0, clk_cap;
logic [3:0] cnt = 0, d = 0, want = 0;
int late = 0, early = 0, window = 0;
time t_d = 0, t_edge = -1000000;
always #(PERIOD/2) clk = ~clk;
assign #(SKEW) clk_cap = clk;
always @(posedge clk) cnt <= #(TCQ) cnt + 1; // launch flop, clock-to-Q
always @(cnt) d <= #(DLY) cnt; // the logic: a pure transport delay
always @(d) begin // hold window: D must not move within TH after the edge
t_d = $time;
if ($time - t_edge < TH) window++;
end
always @(posedge clk_cap) begin // edge k should capture the value launched at edge k-1
t_edge = $time;
if ($time - t_d < TSU) window++; // setup window
if (d == want - 4'd1) late++; // an older value: setup failed
else if (d == want + 4'd1) early++; // the next value: hold failed
want = want + 4'd1;
end
endmodule
module tb;
// The fix: a skew inside the budget. Setup needs at least 100 ps; hold allows at most 250 ps.
path #(.PERIOD(1000), .DLY(600), .SKEW(150)) long150 ();
path #(.PERIOD(1000), .DLY(50), .SKEW(150)) short150 ();
initial begin
#40000;
$display("skew 150: long path window=%0d late=%0d, short path window=%0d early=%0d", long150.window, long150.late, short150.window, short150.early);
if (long150.window + long150.late + short150.window + short150.early == 0) $display("PASS: 150 ps of skew meets setup on the long path and hold on the short one");
$finish;
end
endmodule
Prints: skew 150: long path window=0 late=0, short path window=0 early=0 PASS: 150 ps of skew meets setup on the long path and hold on the short one
Half-Truth
"Skew is always bad; the clock tree should make it zero."
Zero skew is a common target, but useful skew deliberately shifts time between stages. Skew is a tool with a budget, not a defect.
Source Lesson L5.4 review claims (useful skew trades setup time between adjacent stages)