Interview Question · Code Reading
Where to Put the Clock Gate
The Question
The interviewer asks
The same enable drives two clock-gating cells below: one near the clock root and one near the leaves. Which gate's enable path is harder to time, and why?
wire cr, ga, gb, u1, u2, u3, en, eq;
sky130_fd_sc_hd__clkbuf_4 root (.A(clk), .X(cr));
sky130_fd_sc_hd__dlclkp_1 icg_root (.CLK(cr), .GATE(en), .GCLK(ga)); // near the root
sky130_fd_sc_hd__clkbuf_4 ub1 (.A(cr), .X(u1));
sky130_fd_sc_hd__clkbuf_1 ub2 (.A(u1), .X(u2));
sky130_fd_sc_hd__dlclkp_1 icg_leaf (.CLK(u2), .GATE(en), .GCLK(gb)); // near the leaves
sky130_fd_sc_hd__dfxtp_1 ef (.CLK(u3), .D(e0), .Q(eq)); // launches enYou have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The gate near the root. Its clock pin sees the clock early, while the enable is launched by a flop deep in the tree. So the enable path faces negative skew and must still meet the gate's own setup check. In lesson L5.6 the root gate failed by 0.1466 ns and the leaf gate passed with 0.0715 ns. A gate near the root saves more clock power, so the choice is power against enable timing.
en, the enable from ef. Both ICGs check the same en.- Near the root
icg_rootsees the edge at 0.1440 ns,efat 0.4562 ns: skew -0.3122 ns. - Near the leaves
icg_leafshares two buffers withefand sees the edge at 0.3560 ns: skew -0.1002 ns.
Read the diagram as text
- root clkbuf_4: after the port
- icg_root: CLK at the root
- ub1 → ub2: two buffers
- icg_leaf: CLK one level up
- ub3 → ef: launches en
- fa0, fa1: behind 3 buffers
- fb0, fb1: behind 1 buffer
- root clkbuf_4 → icg_root: CLK
- root clkbuf_4 → ub1 → ub2: clock
- ub1 → ub2 → icg_leaf: CLK
- ub1 → ub2 → ub3 → ef: clock
- icg_root → fa0, fa1: GCLK
- icg_leaf → fb0, fb1: GCLK
- ub3 → ef → icg_leaf: en
Latencies from the two paths below. Closer to the root gates more of the tree, and costs the enable more time.
ef launches; four gates make en; the check is at icg_root/GATE. The clock is propagated through the hand-built tree.ef → icg_rootsetup check, latest arrival5 cells
- Clock latency
- Cell delay
- Setup time
- A leaf launches
efsits three buffers down the tree: its clock arrives at 0.4562 ns. - Near the root
The ICG takes its clock right after the root buffer, at 0.1440 ns.
- Violated
The capture edge is 0.3122 ns earlier than the launch edge. Slack -0.1466 ns.
Read the path as a table
Launch: clk rise edge at 0.0000 ns, clock latency 0.4562 ns. Capture: clk rise edge at 1.0000 ns, latency 0.1440 ns, library setup time −0.1411 ns.
Arrival 1.1495 ns, required 1.0028 ns, slack −0.1466 ns (violated).
| Cell | Arc | Through | Edge | Delay (ns) | Time (ns) | Slew (ns) |
|---|---|---|---|---|---|---|
| 1 | ef/CLK → ef/Q | dfxtp_1 | fall | 0.3025 | 0.7587 | 0.0345 |
ef/Q → e1/A | wire eq | fall | 0.0000 | 0.7587 | 0.0345 | |
| 2 | e1/A → e1/Y | inv_1 | rise | 0.0417 | 0.8004 | 0.0308 |
e1/Y → e2/A | wire n1 | rise | 0.0000 | 0.8004 | 0.0308 | |
| 3 | e2/A → e2/Y | nand2_1 | fall | 0.0366 | 0.8369 | 0.0272 |
e2/Y → e3/A | wire n2 | fall | 0.0000 | 0.8369 | 0.0272 | |
| 4 | e3/A → e3/Y | nor2_1 | rise | 0.1113 | 0.9482 | 0.1078 |
e3/Y → e4/A | wire n3 | rise | 0.0000 | 0.9482 | 0.1078 | |
| 5 | e4/A → e4/X | xor2_1 | rise | 0.2013 | 1.1495 | 0.1911 |
e4/X → icg_root/GATE | wire en | rise | 0.0000 | 1.1495 | 0.1911 |
The report
Startpoint: ef (rising edge-triggered flip-flop clocked by clk)
Endpoint: icg_root (rising clock gating-check end-point clocked by clk)
Path Group: gateRoot
Path Type: max
Fanout Cap Slew Delay Time Description
-------------------------------------------------------------------------------------
0.0000 0.0000 clock clk (rise edge)
0.0000 0.0000 clock source latency
1 0.0022 0.1000 0.0000 0.0000 ^ clk (in)
clk (net)
0.1000 0.0000 0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
2 0.0065 0.0392 0.1440 0.1440 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
cr (net)
0.0392 0.0000 0.1440 ^ ub1/A (sky130_fd_sc_hd__clkbuf_4)
1 0.0022 0.0272 0.1082 0.2522 ^ ub1/X (sky130_fd_sc_hd__clkbuf_4)
u1 (net)
0.0272 0.0000 0.2522 ^ ub2/A (sky130_fd_sc_hd__clkbuf_1)
2 0.0065 0.0876 0.1039 0.3560 ^ ub2/X (sky130_fd_sc_hd__clkbuf_1)
u2 (net)
0.0876 0.0000 0.3560 ^ ub3/A (sky130_fd_sc_hd__clkbuf_1)
2 0.0038 0.0568 0.1002 0.4562 ^ ub3/X (sky130_fd_sc_hd__clkbuf_1)
u3 (net)
0.0568 0.0000 0.4562 ^ ef/CLK (sky130_fd_sc_hd__dfxtp_1)
2 0.0044 0.0345 0.3025 0.7587 v ef/Q (sky130_fd_sc_hd__dfxtp_1)
eq (net)
0.0345 0.0000 0.7587 v e1/A (sky130_fd_sc_hd__inv_1)
1 0.0024 0.0308 0.0417 0.8004 ^ e1/Y (sky130_fd_sc_hd__inv_1)
n1 (net)
0.0308 0.0000 0.8004 ^ e2/A (sky130_fd_sc_hd__nand2_1)
1 0.0023 0.0272 0.0366 0.8369 v e2/Y (sky130_fd_sc_hd__nand2_1)
n2 (net)
0.0272 0.0000 0.8369 v e3/A (sky130_fd_sc_hd__nor2_1)
1 0.0045 0.1078 0.1113 0.9482 ^ e3/Y (sky130_fd_sc_hd__nor2_1)
n3 (net)
0.1078 0.0000 0.9482 ^ e4/A (sky130_fd_sc_hd__xor2_1)
3 0.0070 0.1911 0.2013 1.1495 ^ e4/X (sky130_fd_sc_hd__xor2_1)
en (net)
0.1911 0.0000 1.1495 ^ icg_root/GATE (sky130_fd_sc_hd__dlclkp_1)
1.1495 data arrival time
1.0000 1.0000 clock clk (rise edge)
0.0000 1.0000 clock source latency
1 0.0022 0.1000 0.0000 1.0000 ^ clk (in)
clk (net)
0.1000 0.0000 1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
2 0.0065 0.0392 0.1440 1.1440 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
cr (net)
0.0392 0.0000 1.1440 ^ icg_root/CLK (sky130_fd_sc_hd__dlclkp_1)
0.0000 1.1440 clock reconvergence pessimism
-0.1411 1.0028 library setup time
1.0028 data required time
-------------------------------------------------------------------------------------
1.0028 data required time
-1.1495 data arrival time
-------------------------------------------------------------------------------------
-0.1466 slack (VIOLATED)The enable path into the gate near the root. Its clock arrives early, so the enable misses by 0.1466 ns.
The gating tree from lesson L5.6: clock-gating setup checks on both gates and a mux-based enable path.
create_clock -name clk -period 1.0 [get_ports clk]
set_propagated_clock [all_clocks]
set_input_transition 0.1 [get_ports clk]
group_path -name gateRoot -to [get_pins icg_root/GATE]
group_path -name gateLeaf -to [get_pins icg_leaf/GATE]
group_path -name mux -to [get_pins mf/D]
Prints: 0.0715 slack (MET) -0.1466 slack (VIOLATED) -0.1325 slack (VIOLATED)
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer finds the clock-gating check on the enable pin of the gate. It explains the negative skew: the flop that launches the enable sees the clock later than the gate does.
What Interviewers Listen For (Senior)
A good senior answer weighs the power saved near the root against the enable timing. It plans the enable logic, or a copy of the gate for each branch. It also checks paths between gated and ungated flops.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfBreak ItCompare
- Where to Put the Clock Gate
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WhyThe Clock-Gating CheckL2 Mid-Level
What does the timer check on the enable pin of an integrated clock gate?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A setup and a hold check on the enable against the gate's clock, like a flop's data pin. The enable must settle before the clock rises, so the latch inside captures it cleanly. It must not change too soon after. In the sky130 cell the enable setup time ranges from about 0.04 to 0.32 ns depending on the slews.
Self-Check
Tick each key point you covered in your answer.
-
Break ItGating a Clock with a Plain AND GateL1 JuniorL2 Mid-Level
What breaks if someone replaces the integrated clock gate with a plain AND of the clock and the enable?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
If the enable changes while the clock is high, the AND output pulses or cuts the high phase short. Flops may count that glitch as a clock edge. The integrated cell latches the enable while the clock is low. So the enable can only change the output during the low phase. The RTL track's lesson R2.3 shows the glitch in simulation.
An Enable That Changes While Clk Is HighArrows show signals. The enable comes from a flop clocked by clk, so it changes just after each rising edge. Illustrative sequenceCallValueReturnWaiting- Edge k
clkrises whileenis 0, sogclkstays low. The en flop takes its new value at this edge. - 1 ns later
enrises whileclkis still high. The AND output rises with it: an edge the clock never had. The bank writes.Follow the calls, values and waits
- data en rises: en flop → AND gate
- data extra edge: AND gate → wptr and 8 entries
- Edge k+1
clkrises withenat 1: the write that was meant. The data has not changed yet, so it is written twice.
Read the diagram as text
- en flop: changes after each edge
- clk: high for half a period
- AND gate: gclk = clk & en
- wptr and 8 entries: clocked by gclk
- en flop → AND gate: en
- clk → AND gate: clk
- AND gate → wptr and 8 entries: gclk
From RTL lesson R2.3: the enable changes while the clock is high, and the AND makes an extra clock edge.
Self-Check
Tick each key point you covered in your answer.
- Edge k
-
CompareClock Gating vs a Recirculating MuxL1 JuniorL2 Mid-Level
Compare gating the clock of a register bank with holding its value through a feedback mux on each flop.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The mux keeps the clock running and selects the old value when the enable is low. The flops and the clock tree still burn power every cycle, and each flop gains a mux. Clock gating stops the clock to the whole bank with one cell. That saves power but puts a timed enable into the clock tree. In lesson L5.6 the mux path also failed setup, by 0.1325 ns, because the enable arrives late.
Timing pathEnable into a Flop Through a Mux ef → mfsetup check, latest arrival6 cells
- Clock latency
- Cell delay
- Setup time
Read the path as a table
Launch: clk rise edge at 0.0000 ns, clock latency 0.4562 ns. Capture: clk rise edge at 1.0000 ns, latency 0.4562 ns, library setup time −0.1101 ns.
Arrival 1.4786 ns, required 1.3461 ns, slack −0.1325 ns (violated).
Cell Arc Through Edge Delay (ns) Time (ns) Slew (ns) 1 ef/CLK→ef/Qdfxtp_1 fall 0.3025 0.7587 0.0345 ef/Q→e1/Awire eq fall 0.0000 0.7587 0.0345 2 e1/A→e1/Yinv_1 rise 0.0417 0.8004 0.0308 e1/Y→e2/Awire n1 rise 0.0000 0.8004 0.0308 3 e2/A→e2/Ynand2_1 fall 0.0366 0.8369 0.0272 e2/Y→e3/Awire n2 fall 0.0000 0.8369 0.0272 4 e3/A→e3/Ynor2_1 rise 0.1113 0.9482 0.1078 e3/Y→e4/Awire n3 rise 0.0000 0.9482 0.1078 5 e4/A→e4/Xxor2_1 rise 0.2013 1.1495 0.1911 e4/X→mx/Swire en rise 0.0000 1.1495 0.1911 6 mx/S→mx/Xmux2_1 fall 0.3291 1.4786 0.0503 mx/X→mf/Dwire dm fall 0.0000 1.4786 0.0503 The report
Startpoint: ef (rising edge-triggered flip-flop clocked by clk) Endpoint: mf (rising edge-triggered flip-flop clocked by clk) Path Group: mux Path Type: max Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------------- 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock source latency 1 0.0022 0.1000 0.0000 0.0000 ^ clk (in) clk (net) 0.1000 0.0000 0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4) 2 0.0065 0.0392 0.1440 0.1440 ^ root/X (sky130_fd_sc_hd__clkbuf_4) cr (net) 0.0392 0.0000 0.1440 ^ ub1/A (sky130_fd_sc_hd__clkbuf_4) 1 0.0022 0.0272 0.1082 0.2522 ^ ub1/X (sky130_fd_sc_hd__clkbuf_4) u1 (net) 0.0272 0.0000 0.2522 ^ ub2/A (sky130_fd_sc_hd__clkbuf_1) 2 0.0065 0.0876 0.1039 0.3560 ^ ub2/X (sky130_fd_sc_hd__clkbuf_1) u2 (net) 0.0876 0.0000 0.3560 ^ ub3/A (sky130_fd_sc_hd__clkbuf_1) 2 0.0038 0.0568 0.1002 0.4562 ^ ub3/X (sky130_fd_sc_hd__clkbuf_1) u3 (net) 0.0568 0.0000 0.4562 ^ ef/CLK (sky130_fd_sc_hd__dfxtp_1) 2 0.0044 0.0345 0.3025 0.7587 v ef/Q (sky130_fd_sc_hd__dfxtp_1) eq (net) 0.0345 0.0000 0.7587 v e1/A (sky130_fd_sc_hd__inv_1) 1 0.0024 0.0308 0.0417 0.8004 ^ e1/Y (sky130_fd_sc_hd__inv_1) n1 (net) 0.0308 0.0000 0.8004 ^ e2/A (sky130_fd_sc_hd__nand2_1) 1 0.0023 0.0272 0.0366 0.8369 v e2/Y (sky130_fd_sc_hd__nand2_1) n2 (net) 0.0272 0.0000 0.8369 v e3/A (sky130_fd_sc_hd__nor2_1) 1 0.0045 0.1078 0.1113 0.9482 ^ e3/Y (sky130_fd_sc_hd__nor2_1) n3 (net) 0.1078 0.0000 0.9482 ^ e4/A (sky130_fd_sc_hd__xor2_1) 3 0.0070 0.1911 0.2013 1.1495 ^ e4/X (sky130_fd_sc_hd__xor2_1) en (net) 0.1911 0.0000 1.1495 ^ mx/S (sky130_fd_sc_hd__mux2_1) 1 0.0017 0.0503 0.3291 1.4786 v mx/X (sky130_fd_sc_hd__mux2_1) dm (net) 0.0503 0.0000 1.4786 v mf/D (sky130_fd_sc_hd__dfxtp_1) 1.4786 data arrival time 1.0000 1.0000 clock clk (rise edge) 0.0000 1.0000 clock source latency 1 0.0022 0.1000 0.0000 1.0000 ^ clk (in) clk (net) 0.1000 0.0000 1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4) 2 0.0065 0.0392 0.1440 1.1440 ^ root/X (sky130_fd_sc_hd__clkbuf_4) cr (net) 0.0392 0.0000 1.1440 ^ ub1/A (sky130_fd_sc_hd__clkbuf_4) 1 0.0022 0.0272 0.1082 1.2522 ^ ub1/X (sky130_fd_sc_hd__clkbuf_4) u1 (net) 0.0272 0.0000 1.2522 ^ ub2/A (sky130_fd_sc_hd__clkbuf_1) 2 0.0065 0.0876 0.1039 1.3560 ^ ub2/X (sky130_fd_sc_hd__clkbuf_1) u2 (net) 0.0876 0.0000 1.3560 ^ ub3/A (sky130_fd_sc_hd__clkbuf_1) 2 0.0038 0.0568 0.1002 1.4562 ^ ub3/X (sky130_fd_sc_hd__clkbuf_1) u3 (net) 0.0568 0.0000 1.4562 ^ mf/CLK (sky130_fd_sc_hd__dfxtp_1) 0.0000 1.4562 clock reconvergence pessimism -0.1101 1.3461 library setup time 1.3461 data required time ------------------------------------------------------------------------------------- 1.3461 data required time -1.4786 data arrival time ------------------------------------------------------------------------------------- -0.1325 slack (VIOLATED)The same late enable into a flop through a mux. It fails setup by 0.1325 ns.
Self-Check
Tick each key point you covered in your answer.
-
What IfBuilding the Tree Through a Clock GateL2 Mid-LevelL3 Senior
What happens to the clock tree when one gate drives all 52 flops of a block?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
CTS builds the tree on the gated clock after the gate, so the gate's delay adds to every gated flop's latency. In lesson L5.6 the gated MAC's latency was about 0.47 ns against about 0.31 ns ungated. Paths between gated and ungated flops then see that difference as skew and must meet setup and hold.
Self-Check
Tick each key point you covered in your answer.
What People Get Wrong
Common wrong answers and why they fail.
Misconception
"A clock gate is just an AND gate on the clock."
A bare AND can glitch when the enable changes while the clock is high. The library's integrated gate latches the enable while the clock is low. STA times its enable with a setup and hold check.
Source sky130_fd_sc_hd__tt_025C_1v80.lib, dlclkp_1 (clock_gating_integrated_cell latch_posedge); ASIC Point lesson L5.6
Half-Truth
"Gating near the leaves is always better because it times easily."
It times easily but saves less: every buffer above the gate still switches each cycle. Where the enable can be made early, gating near the root saves more power.