Interview Question · Debug
Hold Failures That Appear After CTS
The Question
The interviewer asks
Input-to-register hold passed after placement and fails right after CTS, while internal paths barely moved. The measured numbers are below. Why?
MAC, 5 ns, input delay 1.0 max / 0.1 min, hold repair off (lesson L5.3, measured)
after placement (ideal) after CTS (propagated)
in2reg hold 0.2053 -0.1258 capture latency 0.3116
reg2out setup 3.5883 3.2505 launch latency 0.3042
reg2reg setup 0.1639 0.1356You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Making the clock real adds about 0.31 ns of insertion delay to every flop. Internal paths see it at launch and capture, so it cancels. But an input is referenced to the clock at the port, with no tree in front of it. So the capture flop's clock arrives 0.31 ns later relative to the data, and hold loses that much. Outputs lose setup the same way. Model the agreed external clock, for example with source latency on a virtual clock, instead of fixing it with delay cells.
- Ideal
Both edges at 0 ns: the external flop launches and the capture flop samples at the same instant.
- Propagated
The capture edge moves to Lins after the tree. The launch edge outside does not move.
- The effect
The capture edge is later: the input path gains Lins of setup and loses Lins of hold. An output path is the mirror image: it loses setup and gains hold.
Read the diagram as text
- external flop: edge at 0 ns
- input port: input delay
- capture flop: inside the MAC
- clk port: edge at 0 ns
- clock tree: L_{ins} ≈ 0.31 ns
- external flop → input port: data
- input port → capture flop: data
- clk port → clock tree: clock
- clock tree → capture flop: CLK
Lins is the insertion delay of the tree, from the clk port to the flop.
en to a flop of the MAC, with the input delay of the SDC and the clock propagated through the new tree.en → _797_hold check, earliest arrival1 cell
- Clock latency
- Cell delay
- Wire delay
- Input delay
- Hold time
- The outside edge
The input delay counts from the clock edge at the external flop. That edge has no tree in this block, so it stays at 0 ns.
- Short data path
The minimum input delay of 0.1 ns and a short path: the data arrives at 0.1579 ns.
- A late capture edge
The capture flop sees the edge through the tree, at 0.3116 ns, and its old data must hold until then.
- Violated
Hold slack -0.1258 ns.
Read the path as a table
Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns. Capture: clk rise edge at 0.0000 ns, latency 0.3116 ns, library hold time −0.0279 ns.
Arrival 0.1579 ns, required 0.2837 ns, slack −0.1258 ns (violated).
| Cell | Arc | Through | Edge | Delay (ns) | Time (ns) | Slew (ns) |
|---|---|---|---|---|---|---|
en → _700_/A1 | wire en | rise | 0.0121 | 0.1121 | 0.0243 | |
| 1 | _700_/A1 → _700_/Y | a21oi_1 | fall | 0.0457 | 0.1579 | 0.0328 |
_700_/Y → _797_/D | wire _006_ | fall | 0.0001 | 0.1579 | 0.0328 |
The report
Startpoint: en (input port clocked by clk)
Endpoint: _797_ (rising edge-triggered flip-flop clocked by clk)
Path Group: in2reg
Path Type: min
Fanout Cap Slew Delay Time Description
-------------------------------------------------------------------------------------
0.0000 0.0000 clock clk (rise edge)
0.0000 0.0000 clock network delay (propagated)
0.1000 0.1000 ^ input external delay
69 0.2810 0.0000 0.0000 0.1000 ^ en (in)
en (net)
0.0243 0.0121 0.1121 ^ _700_/A1 (sky130_fd_sc_hd__a21oi_1)
1 0.0026 0.0328 0.0457 0.1579 v _700_/Y (sky130_fd_sc_hd__a21oi_1)
_006_ (net)
0.0328 0.0001 0.1579 v _797_/D (sky130_fd_sc_hd__dfrtp_1)
0.1579 data arrival time
0.0000 0.0000 clock clk (rise edge)
0.0000 0.0000 clock source latency
1 0.0254 0.0000 0.0000 0.0000 ^ clk (in)
clk (net)
0.0004 0.0002 0.0002 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_8)
4 0.0309 0.0676 0.1297 0.1299 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_8)
clknet_0_clk (net)
0.0676 0.0007 0.1306 ^ clkbuf_2_1__f_clk/A (sky130_fd_sc_hd__clkbuf_8)
14 0.0526 0.1017 0.1798 0.3103 ^ clkbuf_2_1__f_clk/X (sky130_fd_sc_hd__clkbuf_8)
clknet_2_1__leaf_clk (net)
0.1017 0.0012 0.3116 ^ _797_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.0000 0.3116 clock reconvergence pessimism
-0.0279 0.2837 library hold time
0.2837 data required time
-------------------------------------------------------------------------------------
0.2837 data required time
-0.1579 data arrival time
-------------------------------------------------------------------------------------
-0.1258 slack (VIOLATED)The worst input hold path after CTS on lesson L5.3's MAC. The tree delays the capture clock, so hold fails.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says the clock now arrives late at every flop. It says this hurts the hold of inputs and the setup of outputs.
What Interviewers Listen For (Senior)
A good senior answer rewrites the I/O constraints against the agreed external timing. It tells a constraint fix apart from a real short path. It removes only the uncertainty that the real clock tree now models.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyProve ItCompareScale It
- Hold Failures That Appear After CTS
-
WhyWhy Common Latency Cancels Inside a BlockL1 Junior
Why did the register-to-register paths barely change when the clock became propagated?
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Reveal the Model Answer
The launch and capture flops both sit behind the same tree. So both edges move later by nearly the same amount. The difference, the local skew, stays small. What changed slightly was skew and the slew-dependent clock-to-Q, 0.1639 to 0.1356 ns in the lesson. Paths that start or end at a port have no tree on the far side, so for them nothing cancels.
Timing pathThe Worst Flop-to-Flop Path After CTS _809_ → _827_setup check, latest arrival16 cells
- Clock latency
- Cell delay
- Wire delay
- Setup time
Read the path as a table
Launch: clk rise edge at 0.0000 ns, clock latency 0.3122 ns. Capture: clk rise edge at 5.0000 ns, latency 0.3067 ns, library setup time −0.0690 ns.
Arrival 5.1021 ns, required 5.2377 ns, slack 0.1356 ns (met).
Cell Arc Through Edge Delay (ns) Time (ns) Slew (ns) 1 _809_/CLK→_809_/Qdfrtp_1 fall 0.4255 0.7377 0.0843 _809_/Q→_607_/Awire acc[1] fall 0.0002 0.7380 0.0843 2 _607_/A→_607_/Yxnor2_1 rise 0.2389 0.9769 0.2165 _607_/Y→_619_/A2wire _080_ rise 0.0001 0.9770 0.2165 3 _619_/A2→_619_/Yo21ai_0 fall 0.1857 1.1627 0.1520 _619_/Y→_641_/Cwire _081_ fall 0.0002 1.1629 0.1520 4 _641_/C→_641_/Xmaj3_1 fall 0.4300 1.5929 0.1029 _641_/X→_663_/Cwire _083_ fall 0.0003 1.5932 0.1029 5 _663_/C→_663_/Xmaj3_1 fall 0.4108 2.0040 0.1011 _663_/X→_685_/Cwire _085_ fall 0.0002 2.0042 0.1011 6 _685_/C→_685_/Xmaj3_1 fall 0.4114 2.4156 0.1020 _685_/X→_707_/Cwire _087_ fall 0.0002 2.4159 0.1020 7 _707_/C→_707_/Xmaj3_1 fall 0.4220 2.8379 0.1115 _707_/X→_727_/A1wire _089_ fall 0.0003 2.8382 0.1115 8 _727_/A1→_727_/Ya211oi_1 rise 0.3022 3.1403 0.2874 _727_/Y→_729_/A3wire _093_ rise 0.0001 3.1404 0.2874 9 _729_/A3→_729_/Yo31ai_1 fall 0.1740 3.3144 0.1185 _729_/Y→_731_/A2wire _095_ fall 0.0004 3.3148 0.1185 10 _731_/A2→_731_/Xo211a_1 fall 0.2487 3.5635 0.0555 _731_/X→_734_/A3wire _097_ fall 0.0002 3.5637 0.0555 11 _734_/A3→_734_/Yo311ai_0 rise 0.5547 4.1184 0.6401 _734_/Y→_736_/A3wire _100_ rise 0.0003 4.1186 0.6401 12 _736_/A3→_736_/Ya31oi_1 fall 0.2350 4.3536 0.1623 _736_/Y→_737_/A2wire _101_ fall 0.0002 4.3538 0.1623 13 _737_/A2→_737_/Ya21oi_1 rise 0.3087 4.6625 0.2733 _737_/Y→_740_/A2wire _102_ rise 0.0002 4.6627 0.2733 14 _740_/A2→_740_/Ya211oi_1 fall 0.1914 4.8541 0.1364 _740_/Y→_742_/Cwire _105_ fall 0.0002 4.8544 0.1364 15 _742_/C→_742_/Ynand3_1 rise 0.1309 4.9853 0.0837 _742_/Y→_748_/Bwire _107_ rise 0.0001 4.9854 0.0837 16 _748_/B→_748_/Yxnor2_1 rise 0.1167 5.1020 0.1180 _748_/Y→_827_/Dwire _048_ rise 0.0001 5.1021 0.1180 The report
Startpoint: _809_ (rising edge-triggered flip-flop clocked by clk) Endpoint: _827_ (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------------- 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock source latency 1 0.0254 0.0000 0.0000 0.0000 ^ clk (in) clk (net) 0.0004 0.0002 0.0002 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_8) 4 0.0309 0.0676 0.1297 0.1299 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_8) clknet_0_clk (net) 0.0676 0.0007 0.1306 ^ clkbuf_2_1__f_clk/A (sky130_fd_sc_hd__clkbuf_8) 14 0.0526 0.1017 0.1798 0.3103 ^ clkbuf_2_1__f_clk/X (sky130_fd_sc_hd__clkbuf_8) clknet_2_1__leaf_clk (net) 0.1017 0.0019 0.3122 ^ _809_/CLK (sky130_fd_sc_hd__dfrtp_1) 4 0.0132 0.0843 0.4255 0.7377 v _809_/Q (sky130_fd_sc_hd__dfrtp_1) acc[1] (net) 0.0843 0.0002 0.7380 v _607_/A (sky130_fd_sc_hd__xnor2_1) 2 0.0080 0.2165 0.2389 0.9769 ^ _607_/Y (sky130_fd_sc_hd__xnor2_1) _080_ (net) 0.2165 0.0001 0.9770 ^ _619_/A2 (sky130_fd_sc_hd__o21ai_0) 2 0.0106 0.1520 0.1857 1.1627 v _619_/Y (sky130_fd_sc_hd__o21ai_0) _081_ (net) 0.1520 0.0002 1.1629 v _641_/C (sky130_fd_sc_hd__maj3_1) 2 0.0102 0.1029 0.4300 1.5929 v _641_/X (sky130_fd_sc_hd__maj3_1) _083_ (net) 0.1029 0.0003 1.5932 v _663_/C (sky130_fd_sc_hd__maj3_1) 2 0.0098 0.1011 0.4108 2.0040 v _663_/X (sky130_fd_sc_hd__maj3_1) _085_ (net) 0.1011 0.0002 2.0042 v _685_/C (sky130_fd_sc_hd__maj3_1) 2 0.0100 0.1020 0.4114 2.4156 v _685_/X (sky130_fd_sc_hd__maj3_1) _087_ (net) 0.1020 0.0002 2.4159 v _707_/C (sky130_fd_sc_hd__maj3_1) 3 0.0121 0.1115 0.4220 2.8379 v _707_/X (sky130_fd_sc_hd__maj3_1) _089_ (net) 0.1115 0.0003 2.8382 v _727_/A1 (sky130_fd_sc_hd__a211oi_1) 2 0.0067 0.2874 0.3022 3.1403 ^ _727_/Y (sky130_fd_sc_hd__a211oi_1) _093_ (net) 0.2874 0.0001 3.1404 ^ _729_/A3 (sky130_fd_sc_hd__o31ai_1) 3 0.0128 0.1185 0.1740 3.3144 v _729_/Y (sky130_fd_sc_hd__o31ai_1) _095_ (net) 0.1185 0.0004 3.3148 v _731_/A2 (sky130_fd_sc_hd__o211a_1) 2 0.0065 0.0555 0.2487 3.5635 v _731_/X (sky130_fd_sc_hd__o211a_1) _097_ (net) 0.0555 0.0002 3.5637 v _734_/A3 (sky130_fd_sc_hd__o311ai_0) 3 0.0112 0.6401 0.5547 4.1184 ^ _734_/Y (sky130_fd_sc_hd__o311ai_0) _100_ (net) 0.6401 0.0003 4.1186 ^ _736_/A3 (sky130_fd_sc_hd__a31oi_1) 2 0.0094 0.1623 0.2350 4.3536 v _736_/Y (sky130_fd_sc_hd__a31oi_1) _101_ (net) 0.1623 0.0002 4.3538 v _737_/A2 (sky130_fd_sc_hd__a21oi_1) 3 0.0118 0.2733 0.3087 4.6625 ^ _737_/Y (sky130_fd_sc_hd__a21oi_1) _102_ (net) 0.2733 0.0002 4.6627 ^ _740_/A2 (sky130_fd_sc_hd__a211oi_1) 4 0.0140 0.1364 0.1914 4.8541 v _740_/Y (sky130_fd_sc_hd__a211oi_1) _105_ (net) 0.1364 0.0002 4.8544 v _742_/C (sky130_fd_sc_hd__nand3_1) 1 0.0050 0.0837 0.1309 4.9853 ^ _742_/Y (sky130_fd_sc_hd__nand3_1) _107_ (net) 0.0837 0.0001 4.9854 ^ _748_/B (sky130_fd_sc_hd__xnor2_1) 1 0.0029 0.1180 0.1167 5.1020 ^ _748_/Y (sky130_fd_sc_hd__xnor2_1) _048_ (net) 0.1180 0.0001 5.1021 ^ _827_/D (sky130_fd_sc_hd__dfrtp_1) 5.1021 data arrival time 5.0000 5.0000 clock clk (rise edge) 0.0000 5.0000 clock source latency 1 0.0254 0.0000 0.0000 5.0000 ^ clk (in) clk (net) 0.0004 0.0002 5.0002 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_8) 4 0.0309 0.0676 0.1297 5.1299 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_8) clknet_0_clk (net) 0.0676 0.0006 5.1305 ^ clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_8) 14 0.0481 0.0945 0.1744 5.3050 ^ clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_8) clknet_2_2__leaf_clk (net) 0.0946 0.0018 5.3067 ^ _827_/CLK (sky130_fd_sc_hd__dfrtp_1) 0.0000 5.3067 clock reconvergence pessimism -0.0690 5.2377 library setup time 5.2377 data required time ------------------------------------------------------------------------------------- 5.2377 data required time -5.1021 data arrival time ------------------------------------------------------------------------------------- 0.1356 slack (MET)The worst flop-to-flop path after CTS. Both clock edges come through the same tree, so the latency mostly cancels.
Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve L5.3.1: Put the External Clock at Its Real EdgeSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
CompareReal Clock vs Virtual Clock for I/OL2 Mid-Level
Compare referencing I/O delays to the block's real clock with referencing them to a virtual clock.
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Reveal the Model Answer
A virtual clock has no source pin in the block; it stands for the clock at the external device. Referenced to the real clock, I/O paths shift when CTS makes that clock propagated, by about the insertion delay. A virtual clock with an agreed source latency keeps the external timing fixed. So the I/O budget means the same before and after CTS.
Timing pathThe Input Path After CTS, with the Virtual-Clock BudgetI/O delays on vclk, which has a source latency of 0.3 ns.Whole pathen → _797_hold check, earliest arrival1 cell
- Clock latency
- Cell delay
- Wire delay
- Input delay
- Hold time
- The outside edge, late too
vclkreaches the external flop at 0.3000 ns. - The tree
The capture flop still sees the edge at 0.3116 ns.
- Met
Hold slack 0.1742 ns. The output path gets its setup back too: 3.5505 ns.
Read the path as a table
Launch: vclk rise edge at 0.0000 ns, clock latency 0.3000 ns. Capture: clk rise edge at 0.0000 ns, latency 0.3116 ns, library hold time −0.0279 ns.
Arrival 0.4579 ns, required 0.2837 ns, slack 0.1742 ns (met).
Cell Arc Through Edge Delay (ns) Time (ns) Slew (ns) en→_700_/A1wire en rise 0.0121 0.4121 0.0243 1 _700_/A1→_700_/Ya21oi_1 fall 0.0457 0.4579 0.0328 _700_/Y→_797_/Dwire _006_ fall 0.0001 0.4579 0.0328 The report
Startpoint: en (input port clocked by vclk) Endpoint: _797_ (rising edge-triggered flip-flop clocked by clk) Path Group: in2reg Path Type: min Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------------- 0.0000 0.0000 clock vclk (rise edge) 0.3000 0.3000 clock network delay (propagated) 0.1000 0.4000 ^ input external delay 69 0.2810 0.0000 0.0000 0.4000 ^ en (in) en (net) 0.0243 0.0121 0.4121 ^ _700_/A1 (sky130_fd_sc_hd__a21oi_1) 1 0.0026 0.0328 0.0457 0.4579 v _700_/Y (sky130_fd_sc_hd__a21oi_1) _006_ (net) 0.0328 0.0001 0.4579 v _797_/D (sky130_fd_sc_hd__dfrtp_1) 0.4579 data arrival time 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock source latency 1 0.0254 0.0000 0.0000 0.0000 ^ clk (in) clk (net) 0.0004 0.0002 0.0002 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_8) 4 0.0309 0.0676 0.1297 0.1299 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_8) clknet_0_clk (net) 0.0676 0.0007 0.1306 ^ clkbuf_2_1__f_clk/A (sky130_fd_sc_hd__clkbuf_8) 14 0.0526 0.1017 0.1798 0.3103 ^ clkbuf_2_1__f_clk/X (sky130_fd_sc_hd__clkbuf_8) clknet_2_1__leaf_clk (net) 0.1017 0.0012 0.3116 ^ _797_/CLK (sky130_fd_sc_hd__dfrtp_1) 0.0000 0.3116 clock reconvergence pessimism -0.0279 0.2837 library hold time 0.2837 data required time ------------------------------------------------------------------------------------- 0.2837 data required time -0.4579 data arrival time ------------------------------------------------------------------------------------- 0.1742 slack (MET)The input path after CTS with a virtual clock and an agreed source latency: hold passes with 0.1742 ns.
Self-Check
Tick each key point you covered in your answer.
-
WhyWhy I/O Paths Shift After CTSL2 Mid-Level
Why do inputs gain setup and lose hold after CTS, when their delays are referenced to the real clock?
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Reveal the Model Answer
After CTS the capture flop sees the clock later, by the insertion delay. The input delay is still counted from the edge at the clock port. So the data has extra time for setup, and hold gets harder by about the same amount. Outputs move the other way.
Self-Check
Tick each key point you covered in your answer.
Missed Corner
"CTS changes only internal paths."
It also moves the clock at every boundary flop. I/O paths referenced to the real clock shift by the insertion delay.
Source Lesson L5.3 key points
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Scale ItHold Budgets at the Chip LevelL3 Senior
Every block team reports input hold violations after CTS. How do you set the I/O clock assumptions for the whole chip so this stops?
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Reveal the Model Answer
Agree one clock model per interface: where each block's clock is assumed to arrive, written as source latency on a virtual clock. Feed the parent's real insertion delays back as they become known. Hold margins stay explicit and owned. Blocks then repair only real short paths, and the top level checks the same interfaces with the real trees.
Self-Check
Tick each key point you covered in your answer.
What People Get Wrong
Common wrong answers and why they fail.
Missed Corner
"Add delay cells on every input until hold passes."
If the external clock is really late too, the violation is a modelling error, not a short path. In lesson L5.3 a budget SDC put source latency on a virtual clock. After CTS it gave input hold 0.1742 ns with no cells added.
Source ASIC Point lesson L5.3 (measured)
Half-Truth
"After CTS remove all clock uncertainty; the clock is real now."
Propagation replaces the skew estimate only. Jitter and margins for effects not modelled stay in the uncertainty.
Source ASIC Point lesson L5.3