Interview Question · Code Reading
Useful Skew: Borrowing Time Between Stages
The Question
The interviewer asks
Stage A into register R fails setup by 0.34 ns, and the stage after R has 0.70 ns to spare. A colleague adds the latency below on R's clock. Does it work, and how far can you push it?
create_clock -name clk -period 1.25 [get_ports clk]
set_clock_transition 0.1 [all_clocks]
set_clock_latency 0.4 [get_pins {r0/CLK r1/CLK}]
group_path -name stageA -to [get_pins r1/D]
group_path -name intoR -to [get_pins r0/D]
group_path -name stageB -to [get_pins b/D]You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Yes: delaying R's clock by 0.4 ns gives stage A 0.4 ns more and takes 0.4 ns from the stage after R, so both pass. The limit is hold into R, which loses the same 0.4 ns; at 0.6 ns stage A gains more but hold into R fails. Around any loop of registers the skews sum to zero. The delay must later be built from real clock cells, in steps.
and2_1.- stage A setup
- stage B setup
- hold into R
- Latency of R 0 sstage A setup = -341.5 ps · stage B setup = 696.4 ps · hold into R = 474.2 ps
No skew: stage A -0.3415 ns, stage B 0.6964 ns, hold into R 0.4742 ns.
- Latency of R 400 psstage A setup = 58.5 ps · stage B setup = 296.4 ps · hold into R = 74.2 ps
0.4 ns: stage A 0.0585 ns, stage B 0.2964 ns, hold 0.0742 ns. Every check passes.
- Latency of R 500 psstage A setup = 158.5 ps · stage B setup = 196.4 ps · hold into R = -25.8 ps
0.5 ns: hold into R is -0.0258 ns. The late edge now catches the next value on the short path.
Read the plot as a table
| Latency of R | stage A setup | stage B setup | hold into R |
|---|---|---|---|
| 0 s | -341.5 ps | 696.4 ps | 474.2 ps |
| 100 ps | -241.5 ps | 596.4 ps | 374.2 ps |
| 200 ps | -141.5 ps | 496.4 ps | 274.2 ps |
| 300 ps | -41.5 ps | 396.4 ps | 174.2 ps |
| 400 ps | 58.5 ps | 296.4 ps | 74.2 ps |
| 400 ps | 58.5 ps | 296.4 ps | 74.2 ps |
| 500 ps | 158.5 ps | 196.4 ps | -25.8 ps |
| 600 ps | 258.5 ps | 96.4 ps | -125.8 ps |
The three checks of this question against the latency on R. At 0.4 ns all pass. Past it, hold into R fails first.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer shows that a later capture clock gives setup time to the stage before. It takes the same time from the stage after. It then checks hold into the delayed register.
What Interviewers Listen For (Senior)
A good senior answer limits the skew by the shortest path into the register, and rules out loops of registers. It plans how to build the delay, and how to cover variation on the branch that is not shared.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyProve ItBreak ItCompare
- Useful Skew: Borrowing Time Between Stages
-
WhyWhy Skew Around a Loop Sums to ZeroL2 Mid-LevelL3 Senior
Why can useful skew not speed up a loop of registers as a whole?
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Reveal the Model Answer
Each register's latency is added to the stage it captures and subtracted from the stage it launches. Walk around a loop and every latency appears once with each sign, so the total time available to the loop is unchanged. The best you can do is share it evenly, so the period is bounded by the loop's average stage delay.
The MAC's Registers and Its One LoopArrows are data. accfeeds the adder that feedsacc.Illustrative sequence- A path that skew can help
p→ adder →acc: delayingaccgives it time, taken from paths that start atacc. - A common vector latency cancels
accis a vector. This path crosses different bits; giving every bit the same latency moves both ends equally.
Read the diagram as text
- ra, rb: operand registers
- multiplier: stage into p
- p: product register
- adder: acc + p
- acc: accumulator
- ra, rb → multiplier: data
- multiplier → p: data
- p → adder: data
- adder → acc: sum
- acc → adder: acc
The MAC has one loop: acc feeds the adder that feeds acc. Skew on acc helps one side of the loop and hurts the other.
Self-Check
Tick each key point you covered in your answer.
- A path that skew can help
-
CompareUseful Skew vs RetimingL2 Mid-LevelL3 Senior
Compare useful skew with retiming, which moves logic across the register instead.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Useful skew moves the clock edge and leaves the logic alone. So it costs clock cells and hold margin, and it is invisible to the RTL. Retiming moves gates across the register, which changes the state encoding and needs equivalence checking and sometimes reset changes. Skew is the late, physical fix. Retiming or pipelining is the structural fix when a stage is too long for any clock trick.
Self-Check
Tick each key point you covered in your answer.
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Break ItBuilding Skew from Real Clock CellsL2 Mid-LevelL3 Senior
The SDC latency of 0.4 ns must now be built from clock delay cells. The measured options are below. Which do you pick?
log R latency built with (propagated clock, lesson L5.4, measured) 2 x clkdlybuf4s18_1 latency 0.3935 ns stage A +0.0399 hold into R +0.0875 1 x clkdlybuf4s50_1 latency 0.4927 ns hold into R -0.0129 1 x clkdlybuf4s25_1 latency 0.2688 ns stage A -0.08332:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Two
clkdlybuf4s18_1cells, the only option that passes both checks. Real cells come in steps, so the built latency rarely matches the SDC number. The window between hold into R and setup of stage A decides which steps are usable. The branch to R is also not shared with the other flops, so its variation is not cancelled by reconvergence pessimism removal.Timing pathStage A with R's Clock Through Two Delay BuffersA propagated clock: every flop's latency is its real clock path. R's clock passes dl1anddl2(clkdlybuf4s18_1).Whole patha1 → r1setup check, latest arrival7 cells
- Clock latency
- Cell delay
- Setup time
- Launch
a0is clocked straight from the port, so its launch latency is 0.0000 ns. - Built latency
R's clock arrives 0.3935 ns late, through the two delay buffers.
- Met
Stage A meets setup with the built delay, at a slack of 0.0399 ns.
Read the path as a table
Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns. Capture: clk rise edge at 1.2500 ns, latency 0.3935 ns, library setup time −0.1217 ns.
Arrival 1.4819 ns, required 1.5218 ns, slack 0.0399 ns (met).
Cell Arc Through Edge Delay (ns) Time (ns) Slew (ns) 1 a1/CLK→a1/Qdfxtp_1 rise 0.4872 0.4872 0.2741 a1/Q→m1/Bwire qa1 rise 0.0000 0.4872 0.2741 2 m1/B→m1/Xxor2_1 fall 0.1173 0.6045 0.0897 m1/X→m2/Awire s1 fall 0.0000 0.6045 0.0897 3 m2/A→m2/Xxor2_1 fall 0.1781 0.7827 0.0897 m2/X→m3/Awire s2 fall 0.0000 0.7827 0.0897 4 m3/A→m3/Xxor2_1 fall 0.1781 0.9608 0.0897 m3/X→m4/Awire s3 fall 0.0000 0.9608 0.0897 5 m4/A→m4/Xxor2_1 fall 0.1781 1.1389 0.0897 m4/X→m5/Awire s4 fall 0.0000 1.1389 0.0897 6 m5/A→m5/Xxor2_1 fall 0.1781 1.3170 0.0897 m5/X→m6/Awire s5 fall 0.0000 1.3170 0.0897 7 m6/A→m6/Xxor2_1 fall 0.1649 1.4819 0.0723 m6/X→r1/Dwire s6 fall 0.0000 1.4819 0.0723 The report
Startpoint: a1 (rising edge-triggered flip-flop clocked by clk) Endpoint: r1 (rising edge-triggered flip-flop clocked by clk) Path Group: stageA Path Type: max Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------------- 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock source latency 4 0.0079 0.1000 0.0000 0.0000 ^ clk (in) clk (net) 0.1000 0.0000 0.0000 ^ a1/CLK (sky130_fd_sc_hd__dfxtp_1) 7 0.0286 0.2741 0.4872 0.4872 ^ a1/Q (sky130_fd_sc_hd__dfxtp_1) qa1 (net) 0.2741 0.0000 0.4872 ^ m1/B (sky130_fd_sc_hd__xor2_1) 1 0.0042 0.0897 0.1173 0.6045 v m1/X (sky130_fd_sc_hd__xor2_1) s1 (net) 0.0897 0.0000 0.6045 v m2/A (sky130_fd_sc_hd__xor2_1) 1 0.0042 0.0897 0.1781 0.7827 v m2/X (sky130_fd_sc_hd__xor2_1) s2 (net) 0.0897 0.0000 0.7827 v m3/A (sky130_fd_sc_hd__xor2_1) 1 0.0042 0.0897 0.1781 0.9608 v m3/X (sky130_fd_sc_hd__xor2_1) s3 (net) 0.0897 0.0000 0.9608 v m4/A (sky130_fd_sc_hd__xor2_1) 1 0.0042 0.0897 0.1781 1.1389 v m4/X (sky130_fd_sc_hd__xor2_1) s4 (net) 0.0897 0.0000 1.1389 v m5/A (sky130_fd_sc_hd__xor2_1) 1 0.0042 0.0897 0.1781 1.3170 v m5/X (sky130_fd_sc_hd__xor2_1) s5 (net) 0.0897 0.0000 1.3170 v m6/A (sky130_fd_sc_hd__xor2_1) 1 0.0017 0.0723 0.1649 1.4819 v m6/X (sky130_fd_sc_hd__xor2_1) s6 (net) 0.0723 0.0000 1.4819 v r1/D (sky130_fd_sc_hd__dfxtp_1) 1.4819 data arrival time 1.2500 1.2500 clock clk (rise edge) 0.0000 1.2500 clock source latency 4 0.0079 0.1000 0.0000 1.2500 ^ clk (in) clk (net) 0.1000 0.0000 1.2500 ^ dl1/A (sky130_fd_sc_hd__clkdlybuf4s18_1) 1 0.0023 0.0352 0.2029 1.4529 ^ dl1/X (sky130_fd_sc_hd__clkdlybuf4s18_1) rc1 (net) 0.0352 0.0000 1.4529 ^ dl2/A (sky130_fd_sc_hd__clkdlybuf4s18_1) 2 0.0038 0.0482 0.1906 1.6435 ^ dl2/X (sky130_fd_sc_hd__clkdlybuf4s18_1) rc2 (net) 0.0482 0.0000 1.6435 ^ r1/CLK (sky130_fd_sc_hd__dfxtp_1) 0.0000 1.6435 clock reconvergence pessimism -0.1217 1.5218 library setup time 1.5218 data required time ------------------------------------------------------------------------------------- 1.5218 data required time -1.4819 data arrival time ------------------------------------------------------------------------------------- 0.0399 slack (MET)Stage A with R's clock through two real delay buffers: setup passes with 0.0399 ns to spare.
Self-Check
Tick each key point you covered in your answer.
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Prove ItSolve L5.4.1: Schedule Three Capture ClocksSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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WhyWhy CPPR Does Not Cover the Delay BranchL2 Mid-LevelL3 Senior
Why is the variation on the branch to R not cancelled by reconvergence pessimism removal?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
CPPR credits only the clock segment that launch and capture share, because one wire cannot be early and late at once. The delay cells sit on the branch to R alone. So the tool still derates them late for one side and early for the other. That variation shrinks the usable window.
Self-Check
Tick each key point you covered in your answer.
Misconception
"CPPR removes all clock variation from the report."
It removes only the shared part. Every cell after the branch point still carries its full derate.
Source Lesson L2.9 key points
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Missed Corner
"More latency on R just makes stage A faster; push it until setup is comfortable."
Hold into R loses whatever stage A gains. At 0.6 ns stage A has 0.26 ns spare but hold into R fails by 0.13 ns; at 0.4 ns every check passes.
Run It
The pipeline from lesson L5.4 with 0.6 ns of latency on R's clock pins.
create_clock -name clk -period 1.25 [get_ports clk]
set_clock_transition 0.1 [all_clocks]
set_clock_latency 0.6 [get_pins {r0/CLK r1/CLK}]
group_path -name stageA -to [get_pins r1/D]
group_path -name intoR -to [get_pins r0/D]
group_path -name stageB -to [get_pins b/D]
Prints: 1.1579 slack (MET) 0.2585 slack (MET) 0.0964 slack (MET) -0.1258 slack (VIOLATED)
See the Fix
create_clock -name clk -period 1.25 [get_ports clk]
set_clock_transition 0.1 [all_clocks]
set_clock_latency 0.4 [get_pins {r0/CLK r1/CLK}]
group_path -name stageA -to [get_pins r1/D]
group_path -name intoR -to [get_pins r0/D]
group_path -name stageB -to [get_pins b/D]
Prints: 0.9579 slack (MET) 0.0585 slack (MET) 0.2964 slack (MET) 0.0742 slack (MET)
Misconception
"Useful skew can fix a slow self-loop too."
A register feeding itself sees the same latency at launch and capture, so the skew is zero by construction. Around any register cycle the skews sum to zero.
Source ASIC Point lesson L5.4 (MAC acc -> acc slack unchanged at -0.0959 ns, measured)