Interview Question · Concept
DRC vs LVS
- Likely at Google
- Likely at Broadcom
- Likely at Micron
The Question
The interviewer asks
What do DRC and LVS each check, and what can a layout pass in one and fail in the other?
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Reveal the Model Answer
DRC checks geometry against the foundry's rule deck: widths, spacings, enclosures and densities. It has no idea what the circuit is meant to do. LVS extracts the devices and connections from the layout and compares them with the reference netlist. Two wires shorted by a legal-looking strap pass DRC and fail LVS. A perfectly connected layout with a spacing error passes LVS and fails DRC.
Read the diagram as text
- Merged layout
- Device extraction
- Reference netlist
- Cell and device definitions
- Compare circuits
- Merged layout → Device extraction: shapes
- Device extraction → Compare circuits: extracted circuit
- Reference netlist → Cell and device definitions: instances
- Cell and device definitions → Compare circuits: reference circuit
Exporting two netlists from the same logical database does not supply physical measurements about the manufactured connections.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Fresher)
A good fresher answer says DRC checks geometry and LVS checks connections. It gives one example of a layout that passes one check and fails the other.
What Interviewers Listen For (Mid-Level)
A good mid-level answer knows the LVS reference must include power pins, and physical-only cells by an agreed rule. It knows neither check says anything about timing or logic equivalence.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItCompare
- DRC vs LVS
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WhyPower Pins and Physical Cells in LVSL1 JuniorL2 Mid-Level
Why does an LVS run fail on a design whose logic netlist is correct?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The logic netlist usually has no power pins and no physical-only cells such as taps, fillers and decaps. The layout has all of them. LVS needs a reference built with the same conventions: supplies connected, physical cells either included or excluded by a documented rule. A mismatch there is a reference problem, not a layout bug.
Self-Check
Tick each key point you covered in your answer.
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Prove ItSolve L7.3.1: Check the Base Cells After an ECOSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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CompareFour Checks, Four QuestionsL1 JuniorL2 Mid-Level
Compare DRC, LVS, logic equivalence and STA: which question does each one answer?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
DRC asks whether the shapes can be manufactured. LVS asks whether the shapes form the netlist you meant. Logic equivalence asks whether that netlist computes the same function as the RTL. STA asks whether it does so fast enough at every corner. A clean report in one says nothing about the other three.
Four Checks, Four QuestionsArrows show which data each check reads. Read the diagram as text
- Layout shapes
- Netlist
- RTL
- DRC: Can the shapes be made?
- LVS: Do the shapes form the netlist?
- Equivalence: Does the netlist match the RTL?
- STA: Is it fast enough at every corner?
- Layout shapes → DRC
- Layout shapes → LVS
- Netlist → LVS
- Netlist → Equivalence
- RTL → Equivalence
- Netlist → STA
A clean report from one check says nothing about the other three.
Self-Check
Tick each key point you covered in your answer.
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What IfEquivalence Run on an Old NetlistL2 Mid-Level
What if LVS passes on the final layout, but equivalence was last run before the final ECO?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Then nothing ties the shipped layout to the RTL. LVS shows that the layout matches the post-ECO netlist. But that netlist was never compared with the RTL. Rerun equivalence on the final netlist, because every check must use the same final data.
Self-Check
Tick each key point you covered in your answer.
Misconception
"LVS passed on the final layout, so the logic is right."
LVS compares the layout with a netlist. It never checks that netlist against the RTL.
Source Lesson L7.5 key points
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What IfWhat a Clean Router Count CoversL2 Mid-Level
Asked if they rely on the router's own DRC count
What if the detailed router reports zero violations? Is the layout DRC clean?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Not necessarily. The router checks the rules it knows from the technology LEF, a subset of the foundry deck. Full DRC on the merged layout, with cells, fill and every rule, is a separate run. Antenna checking is separate again. Sign-off quotes which checker ran with which deck.
Self-Check
Tick each key point you covered in your answer.
What People Get Wrong
Common wrong answers and why they fail.
Misconception
"LVS clean means the chip does what the RTL says."
LVS compares the layout with a netlist. Whether that netlist matches the RTL is logic equivalence, and whether it is fast enough is timing: separate checks.
Source ASIC Point lesson L7.3
Half-Truth
"LVS passed because the device and net counts match."
Counts can match with swapped connections or wrong device sizes. LVS compares connections and device parameters, not totals.
Source ASIC Point lesson L7.3