Corners and Multi-Mode Multi-Corner Analysis

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WhyWhat IfProve ItBreak ItCompareScale It

1. Corners and Multi-Mode Multi-Corner Analysis
2. WhyWhy the Cold Corner Can Be SlowerL2 Mid-Level

   Why can a cold corner be slower than a hot one?

   Reveal the Model Answer

   Temperature moves two things in opposite directions. Carrier mobility falls as it gets hotter, which slows cells. The threshold voltage also falls, which speeds them up. At low supply voltage, where the overdrive above threshold is small, the threshold effect can win, so cells are slower when cold. That is why the corner list includes both temperatures and the result is measured per library.

   ffl → ffcsetup check, latest arrival2 cells

   • Clock latency
   • Cell delay
   • Setup time

   Read the path as a table

   Launch: clk rise edge at 0.0000 ns, clock latency 0.3593 ns. Capture: clk rise edge at 1.0000 ns, latency 0.3593 ns, library setup time −0.2659 ns.

   Arrival 1.0993 ns, required 1.0934 ns, slack −0.0059 ns (violated).

   Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
   1	ffl/CLK → ffl/Q	dfxtp_1	rise	0.6394	0.9987	0.0971
   	ffl/Q → u2/B	wire q1	rise	0.0000	0.9987	0.0971
   2	u2/B → u2/Y	nand2_1	fall	0.1006	1.0993	0.0535
   	u2/Y → ffc/D	wire n2	fall	0.0000	1.0993	0.0535

   The report

   Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
   Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
   Path Group: clk
   Path Type: max
   
   Fanout       Cap      Slew     Delay      Time   Description
   -------------------------------------------------------------------------------------
                                 0.0000    0.0000   clock clk (rise edge)
                                 0.0000    0.0000   clock source latency
        1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                    clk (net)
                       0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
        2    0.0042    0.0568    0.2295    0.2295 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                    cr (net)
                       0.0568    0.0000    0.2295 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
        1    0.0017    0.0560    0.1298    0.3593 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
                                                    cl (net)
                       0.0560    0.0000    0.3593 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
        2    0.0047    0.0971    0.6394    0.9987 ^ ffl/Q (sky130_fd_sc_hd__dfxtp_1)
                                                    q1 (net)
                       0.0971    0.0000    0.9987 ^ u2/B (sky130_fd_sc_hd__nand2_1)
        1    0.0016    0.0535    0.1006    1.0993 v u2/Y (sky130_fd_sc_hd__nand2_1)
                                                    n2 (net)
                       0.0535    0.0000    1.0993 v ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                           1.0993   data arrival time
   
                                 1.0000    1.0000   clock clk (rise edge)
                                 0.0000    1.0000   clock source latency
        1    0.0022    0.1000    0.0000    1.0000 ^ clk (in)
                                                    clk (net)
                       0.1000    0.0000    1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
        2    0.0042    0.0568    0.2295    1.2295 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                    cr (net)
                       0.0568    0.0000    1.2295 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
        1    0.0017    0.0560    0.1298    1.3593 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
                                                    cc (net)
                       0.0560    0.0000    1.3593 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                                 0.0000    1.3593   clock reconvergence pessimism
                                -0.2659    1.0934   library setup time
                                           1.0934   data required time
   -------------------------------------------------------------------------------------
                                           1.0934   data required time
                                          -1.0993   data arrival time
   -------------------------------------------------------------------------------------
                                          -0.0059   slack (VIOLATED)

   The same path at the slow, hot corner: -0.0059 ns. That is better than the cold corner's -0.1328 ns.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Temperature moves two things in opposite directions. Key point 2 Carrier mobility falls as it gets hotter, which slows cells. Key point 3 The threshold voltage also falls, which speeds them up. Key point 4 At low supply voltage, where the overdrive above threshold is small, the threshold effect can win, so cells are slower when cold. Key point 5 That is why the corner list includes both temperatures and the result is measured per library.

   • Lesson L2.9Corners, Derates, OCV and CPPR
   • Lesson E2.7Corners and Temperature
   • Problem L2.9.1A Checker for Timing and Electrical Limits
3. Prove ItSolve L2.9.1: A Checker for Timing and Electrical LimitsSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L2.9.1

4. CompareWhich Corner Is Worst for Setup and for HoldL1 JuniorL2 Mid-Level

   Compare the corners at which setup and hold are usually worst, and say why you check both everywhere.

   Reveal the Model Answer

   Setup is usually worst where cells are slowest: a slow process at low voltage. Hold is usually worst where they are fastest: a fast process at high voltage. In the lesson's small clock tree the fast cold corner had the smallest hold slack, 0.2397 ns, and the slow corners failed setup. Skew and wire delays do not scale like cell delays, so sign-off still runs both checks at every corner.

   ffl → ffchold check, earliest arrival2 cells

   • Clock latency
   • Cell delay
   • Hold time

   Read the path as a table

   Launch: clk rise edge at 0.0000 ns, clock latency 0.1420 ns. Capture: clk rise edge at 0.0000 ns, latency 0.1420 ns, library hold time −0.0167 ns.

   Arrival 0.3650 ns, required 0.1253 ns, slack 0.2397 ns (met).

   Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
   1	ffl/CLK → ffl/Q	dfxtp_1	fall	0.1879	0.3300	0.0247
   	ffl/Q → u2/B	wire q1	fall	0.0000	0.3300	0.0247
   2	u2/B → u2/Y	nand2_1	rise	0.0351	0.3650	0.0210
   	u2/Y → ffc/D	wire n2	rise	0.0000	0.3650	0.0210

   The report

   Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
   Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
   Path Group: clk
   Path Type: min
   
   Fanout       Cap      Slew     Delay      Time   Description
   -------------------------------------------------------------------------------------
                                 0.0000    0.0000   clock clk (rise edge)
                                 0.0000    0.0000   clock source latency
        1    0.0023    0.1000    0.0000    0.0000 ^ clk (in)
                                                    clk (net)
                       0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
        2    0.0045    0.0251    0.0966    0.0966 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                    cr (net)
                       0.0251    0.0000    0.0966 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
        1    0.0019    0.0260    0.0454    0.1420 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
                                                    cl (net)
                       0.0260    0.0000    0.1420 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
        2    0.0044    0.0247    0.1879    0.3300 v ffl/Q (sky130_fd_sc_hd__dfxtp_1)
                                                    q1 (net)
                       0.0247    0.0000    0.3300 v u2/B (sky130_fd_sc_hd__nand2_1)
        1    0.0017    0.0210    0.0351    0.3650 ^ u2/Y (sky130_fd_sc_hd__nand2_1)
                                                    n2 (net)
                       0.0210    0.0000    0.3650 ^ ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                           0.3650   data arrival time
   
                                 0.0000    0.0000   clock clk (rise edge)
                                 0.0000    0.0000   clock source latency
        1    0.0023    0.1000    0.0000    0.0000 ^ clk (in)
                                                    clk (net)
                       0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
        2    0.0045    0.0251    0.0966    0.0966 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                    cr (net)
                       0.0251    0.0000    0.0966 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
        1    0.0019    0.0260    0.0454    0.1420 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
                                                    cc (net)
                       0.0260    0.0000    0.1420 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                                 0.0000    0.1420   clock reconvergence pessimism
                                -0.0167    0.1253   library hold time
                                           0.1253   data required time
   -------------------------------------------------------------------------------------
                                           0.1253   data required time
                                          -0.3650   data arrival time
   -------------------------------------------------------------------------------------
                                           0.2397   slack (MET)

   Hold at the fast, cold corner: 0.2397 ns, the smallest hold slack of the three corners.

   create_clock -name clk -period 1.0 [get_ports clk]
   set_propagated_clock [all_clocks]
   set_input_transition 0.1 [get_ports clk]
   

   Prints: 0.6973 slack (MET) 0.2397 slack (MET)

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Setup is usually worst where cells are slowest: a slow process at low voltage. Key point 2 Hold is usually worst where they are fastest: a fast process at high voltage. Key point 3 In the lesson's small clock tree the fast cold corner had the smallest hold slack, 0.2397 ns, and the slow corners failed setup. Key point 4 Skew and wire delays do not scale like cell delays, so sign-off still runs both checks at every corner.

   • Lesson L2.9Corners, Derates, OCV and CPPR
   • Lesson L7.1Sign-Off Timing: Every Corner, Every Check
5. Scale ItPruning the Mode and Corner MatrixL3 SeniorL4 Staff

   Your chip has five modes and twelve corners. How do you keep sign-off affordable without missing the worst case?

   Reveal the Model Answer

   Start from the full matrix, and drop a view only with evidence that another view always dominates it. Get that evidence by running everything once on an early netlist, for example. Keep every view that is worst for some endpoint group in any check. Optimise on a small set of dominant views, but run the full set at sign-off and after every late change.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Start from the full matrix, and drop a view only with evidence that another view always dominates it. Key point 2 Get that evidence by running everything once on an early netlist, for example. Key point 3 Keep every view that is worst for some endpoint group in any check. Key point 4 Optimise on a small set of dominant views, but run the full set at sign-off and after every late change.

   • Lesson L7.1Sign-Off Timing: Every Corner, Every Check
   • Lesson L7.6The Sign-Off Review
6. What IfHold Repair Across Four CornersL2 Mid-LevelL3 Senior

   Your hold repair passes at the fast corner but fails setup at the slow corner. How do you close both?

   Reveal the Model Answer

   Repair against all required corners at once. Then the tool sees the setup cost at the slow corner when it inserts delay at the fast one. Prefer delay on paths with setup slack to spare at every corner. Fix shared skew in the clock tree before adding cells. A repair that must break setup to fix hold shows the constraints or the clock tree need work, not more cells.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Repair against all required corners at once. Key point 2 Then the tool sees the setup cost at the slow corner when it inserts delay at the fast one. Key point 3 Prefer delay on paths with setup slack to spare at every corner. Key point 4 Fix shared skew in the clock tree before adding cells. Key point 5 A repair that must break setup to fix hold shows the constraints or the clock tree need work, not more cells.

   • Lesson L5.5Hold Repair After CTS
   • Lesson L7.1Sign-Off Timing: Every Corner, Every Check
   • Lesson L2.9Corners, Derates, OCV and CPPR
   • Problem L7.1.1Make the Hold Repair Survive Four Corners
7. Prove ItSolve L7.1.1: Make the Hold Repair Survive Four CornersSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L7.1.1

8. Break ItOne Delay Cell for Forty Hold FixesL2 Mid-LevelL3 Senior

   Break it: the repair fixes forty hold violations with one delay cell on a shared net. What can go wrong?

   Reveal the Model Answer

   The shared net also feeds long paths, and they slow down by the same delay. With tight setup at the slow corner, those paths now fail. Put the delay near each failing D pin instead, where only the short path passes. Then check setup at every corner again.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The shared net also feeds long paths, and they slow down by the same delay. Key point 2 With tight setup at the slow corner, those paths now fail. Key point 3 Put the delay near each failing D pin instead, where only the short path passes. Key point 4 Then check setup at every corner again.

   Half-Truth

   "One cell for forty fixes is always the best repair."

   It is the cheapest in area, but its delay lands on every path through that net. Paths with no setup margin then fail.

   Source Lesson L5.5 key points

   • Lesson L5.5Hold Repair After CTS
   • Lesson L2.9Corners, Derates, OCV and CPPR