Interview Question · Debug
Fixing a Hold Violation
- Likely at Broadcom
- Likely at AMD
The Question
The interviewer asks
After a setup fix that upsized a buffer, the report below shows a hold violation of -0.0207 ns that was not there before. Explain what happened and how you would fix it.
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Reveal the Model Answer
The bigger buffer drives its 17 loads faster, so the shortest path got shorter. The capture clock is still seven buffers late. Hold lost what setup gained. Fix hold by adding delay on the short path near the capture flop, or by reducing the skew. Never fix it by touching the period. Here a smaller buf_2 meets both checks, so pick the smallest drive that closes setup rather than the biggest.
- At the driver
A cell between the port and the shared net slows every path. Fine while flop S has setup slack to give.
- On the shared net
Any delay here also lands on the long branch, so it costs flop S setup time.
- At the D pin of flop H
Only the hold-failing path slows. It needs a cell per endpoint, but setup elsewhere is untouched.
Read the diagram as text
- en port: outside flop
- shared net: fans out
- short branch: one gate
- long branch: deep logic
- flop H: fails hold
- flop S: tight setup
- en port → shared net: data
- shared net → short branch: data
- shared net → long branch: data
- short branch → flop H: D
- long branch → flop S: D
Where hold delay can go. Delay near the failing flop slows only the short path; delay on the shared net slows the long path too.
The hold path after the upsize, measured with OpenSTA 3.1.0 on sky130_fd_sc_hd (our variant of the lesson L2.4 bench):
1 0.0073 0.0818 0.3503 0.3503 ^ ff1/Q (sky130_fd_sc_hd__dfxtp_1)
17 0.0285 0.0591 0.1220 0.4724 ^ db/X (sky130_fd_sc_hd__buf_8)
0.0591 0.0000 0.4724 ^ ff2/D (sky130_fd_sc_hd__dfxtp_1)
0.4724 data arrival time
0.0353 0.0000 0.5286 ^ ff2/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.0355 0.4931 library hold time
0.4931 data required time
-0.0207 slack (VIOLATED)Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer reads the report and sees that the data arrives before the late capture clock plus the hold time. It suggests adding delay on the data path.
What Interviewers Listen For (Senior)
A good senior answer links the violation to the earlier setup fix. It checks the setup margin before adding delay, and puts the delay near the failing D pin. It re-checks hold at the fast corner and after routing.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyProve ItBreak ItCompareScale It
- Fixing a Hold Violation
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WhyWhy Hold Is Repaired After CTSL1 JuniorL2 Mid-Level
Why do flows wait until after clock tree synthesis to repair hold?
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Reveal the Model Answer
Hold slack depends on the real launch and capture latencies, and before CTS the clock is ideal, with zero skew. Repairing earlier would add delay for skew that may never appear and miss the skew that does. In lesson L5.5 no endpoint failed hold with ideal clocks, while 45 failed after CTS.
Self-Check
Tick each key point you covered in your answer.
-
CompareDelay Cells vs Buffer Chains for HoldL1 JuniorL2 Mid-Level
Compare a delay cell with a chain of small buffers as a hold fix.
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Reveal the Model Answer
A delay cell is built to be slow. In sky130,
dlygate4sd3_1gives about 0.53 ns for 10 µm², whilebuf_1gives about 0.08 ns for 3.75 µm². So one delay cell replaces several buffers at far less area per nanosecond. Buffers suit small fixes and are easier to resize later.Timing pathThe Shift Register with a Delay CellThe same five-buffer capture clock; hd1(dlygate4sd3_1) sits between ff1 and ff2.Whole pathff1 → ff2hold check, earliest arrival2 cells
- Clock latency
- Cell delay
- Hold time
- The delay cell
hd1adds 0.5205 ns to the fastest path. - Hold met
Hold slack 0.4835 ns.
Read the path as a table
Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns. Capture: clk rise edge at 0.0000 ns, latency 0.3818 ns, library hold time −0.0326 ns.
Arrival 0.8327 ns, required 0.3492 ns, slack 0.4835 ns (met).
Cell Arc Through Edge Delay (ns) Time (ns) Slew (ns) 1 ff1/CLK→ff1/Qdfxtp_1 rise 0.3123 0.3123 0.0333 ff1/Q→hd1/Awire q1 rise 0.0000 0.3123 0.0333 2 hd1/A→hd1/Xdlygate4sd3_1 rise 0.5205 0.8327 0.0451 hd1/X→ff2/Dwire q1d rise 0.0000 0.8327 0.0451 The report
Startpoint: ff1 (rising edge-triggered flip-flop clocked by clk) Endpoint: ff2 (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------------- 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock source latency 2 0.0041 0.1000 0.0000 0.0000 ^ clk (in) clk (net) 0.1000 0.0000 0.0000 ^ ff1/CLK (sky130_fd_sc_hd__dfxtp_1) 1 0.0017 0.0333 0.3123 0.3123 ^ ff1/Q (sky130_fd_sc_hd__dfxtp_1) q1 (net) 0.0333 0.0000 0.3123 ^ hd1/A (sky130_fd_sc_hd__dlygate4sd3_1) 1 0.0017 0.0451 0.5205 0.8327 ^ hd1/X (sky130_fd_sc_hd__dlygate4sd3_1) q1d (net) 0.0451 0.0000 0.8327 ^ ff2/D (sky130_fd_sc_hd__dfxtp_1) 0.8327 data arrival time 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock source latency 2 0.0041 0.1000 0.0000 0.0000 ^ clk (in) clk (net) 0.1000 0.0000 0.0000 ^ cb1/A (sky130_fd_sc_hd__clkbuf_1) 1 0.0022 0.0395 0.0906 0.0906 ^ cb1/X (sky130_fd_sc_hd__clkbuf_1) ck1 (net) 0.0395 0.0000 0.0906 ^ cb2/A (sky130_fd_sc_hd__clkbuf_1) 1 0.0022 0.0388 0.0736 0.1642 ^ cb2/X (sky130_fd_sc_hd__clkbuf_1) ck2 (net) 0.0388 0.0000 0.1642 ^ cb3/A (sky130_fd_sc_hd__clkbuf_1) 1 0.0022 0.0388 0.0734 0.2376 ^ cb3/X (sky130_fd_sc_hd__clkbuf_1) ck3 (net) 0.0388 0.0000 0.2376 ^ cb4/A (sky130_fd_sc_hd__clkbuf_1) 1 0.0022 0.0388 0.0734 0.3110 ^ cb4/X (sky130_fd_sc_hd__clkbuf_1) ck4 (net) 0.0388 0.0000 0.3110 ^ cb5/A (sky130_fd_sc_hd__clkbuf_1) 1 0.0019 0.0353 0.0708 0.3818 ^ cb5/X (sky130_fd_sc_hd__clkbuf_1) ck5 (net) 0.0353 0.0000 0.3818 ^ ff2/CLK (sky130_fd_sc_hd__dfxtp_1) 0.0000 0.3818 clock reconvergence pessimism -0.0326 0.3492 library hold time 0.3492 data required time ------------------------------------------------------------------------------------- 0.3492 data required time -0.8327 data arrival time ------------------------------------------------------------------------------------- 0.4835 slack (MET)One
dlygate4sd3_1between the two flops of lesson L2.4 turns a failing hold check into 0.4835 ns of slack.Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve L2.4.1: The Smallest Hold RepairSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
Scale ItHold Repair Across Four CornersL2 Mid-LevelL3 Senior
Your hold repair passes at the fast corner but fails setup at the slow corner. How do you close both?
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Reveal the Model Answer
Repair against all required corners at once. Then the tool sees the setup cost at the slow corner when it inserts delay at the fast one. Prefer delay on paths with setup slack to spare at every corner. Fix shared skew in the clock tree before adding cells. A repair that must break setup to fix hold shows the constraints or the clock tree need work, not more cells.
Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve L7.1.1: Make the Hold Repair Survive Four CornersSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
Break ItOne Delay Cell for Forty Hold FixesL2 Mid-LevelL3 Senior
Break it: the repair fixes forty hold violations with one delay cell on a shared net. What can go wrong?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The shared net also feeds long paths, and they slow down by the same delay. With tight setup at the slow corner, those paths now fail. Put the delay near each failing D pin instead, where only the short path passes. Then check setup at every corner again.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"One cell for forty fixes is always the best repair."
It is the cheapest in area, but its delay lands on every path through that net. Paths with no setup margin then fail.
Source Lesson L5.5 key points
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Misconception
"Upsizing a cell can only help timing."
Upsizing speeds the path, which helps setup and hurts hold. Here buf_8 turns a hold slack of +0.0745 ns into -0.0207 ns; buf_2 keeps both checks met.
Run It
The same path with the buffer upsized from buf_1 to buf_8 to win setup.
create_clock -name clk -period 1.0 [get_ports clk]
set_propagated_clock [all_clocks]
set_input_transition 0.1 [get_ports clk]
Prints: 0.4486 slack (MET) 17 0.0285 0.0591 0.1220 0.4724 ^ db/X (sky130_fd_sc_hd__buf_8) -0.0207 slack (VIOLATED)
See the Fix
create_clock -name clk -period 1.0 [get_ports clk]
set_propagated_clock [all_clocks]
set_input_transition 0.1 [get_ports clk]
Prints: 0.4225 slack (MET) 0.0064 slack (MET)
Half-Truth
"Add delay cells anywhere on the path until hold passes."
Delay on a net shared with long paths costs their setup too. Put it near the failing capture pin, and check setup on every path through that pin.
Source ASIC Point lesson L5.5 (measured hold repair on the MAC)
Wrong Altitude
Fixes hold before clock tree synthesis, with ideal clocks.
With ideal clocks there is no skew, so most hold failures do not exist yet. Hold is repaired after CTS, with propagated clocks.