Interview Question · Concept
On-Chip Variation, Derates and CPPR
- Likely at Google
- Likely at Broadcom
- Likely at Intel
The Question
The interviewer asks
What is on-chip variation, and how do derates model it in a setup check? Why does the tool then give some of the margin back?
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Reveal the Model Answer
On-chip variation means two identical cells on one die are not equally fast. For setup, the tool slows the launch clock and data path and speeds up the capture clock. It does the reverse for hold. On the clock buffers both paths share, that would count one buffer as fast and slow at once. So CPPR credits the difference back. In lesson L2.9, ±5 % derates cost about 0.025 ns of setup and returned 0.0138 ns as CPPR.
- Launch side late
For setup, the launch clock and the data path take the late derate: the data arrives as late as it plausibly could.
- Capture side early
The capture clock takes the early derate: the capture edge comes as soon as it plausibly could.
- One buffer, two speeds
rootis on both clock paths, so it is late for the launch and early for the capture in the same check.
Read the diagram as text
- clk port: 0.1 ns slew
- root (clkbuf_4): common to both
- bl (clkbuf_1): setup: late
- bc (clkbuf_1): setup: early
- ffl → u1 → u2: launch and data: late
- ffc: capture: early
- clk port → root (clkbuf_4): clock
- root (clkbuf_4) → bl (clkbuf_1): clock
- root (clkbuf_4) → bc (clkbuf_1): clock
- bl (clkbuf_1) → ffl → u1 → u2: CLK
- bc (clkbuf_1) → ffc: CLK
- ffl → u1 → u2 → ffc: data
Each choice is pessimistic on purpose.
ffl → ffchold check, earliest arrival2 cells
- Clock latency
- Cell delay
- Hold time
Read the path as a table
Launch: clk rise edge at 0.0000 ns, clock latency 0.1967 ns. Capture: clk rise edge at 0.0000 ns, latency 0.2174 ns, library hold time −0.0290 ns.
Arrival 0.5235 ns, required 0.1746 ns, slack 0.3489 ns (met).
| Cell | Arc | Through | Edge | Delay (ns) | Time (ns) | Slew (ns) |
|---|---|---|---|---|---|---|
| 1 | ffl/CLK → ffl/Q | dfxtp_1 | fall | 0.2799 | 0.4766 | 0.0345 |
ffl/Q → u2/B | wire q1 | fall | 0.0000 | 0.4766 | 0.0345 | |
| 2 | u2/B → u2/Y | nand2_1 | rise | 0.0469 | 0.5235 | 0.0281 |
u2/Y → ffc/D | wire n2 | rise | 0.0000 | 0.5235 | 0.0281 |
The report
Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: min
Fanout Cap Slew Delay Time Description
-------------------------------------------------------------------------------------
0.0000 0.0000 clock clk (rise edge)
0.0000 0.0000 clock source latency
1 0.0022 0.1000 0.0000 0.0000 ^ clk (in)
clk (net)
0.1000 0.0000 0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
2 0.0044 0.0334 0.1312 0.1312 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
cr (net)
0.0334 0.0000 0.1312 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
1 0.0019 0.0353 0.0655 0.1967 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
cl (net)
0.0353 0.0000 0.1967 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
2 0.0044 0.0345 0.2799 0.4766 v ffl/Q (sky130_fd_sc_hd__dfxtp_1)
q1 (net)
0.0345 0.0000 0.4766 v u2/B (sky130_fd_sc_hd__nand2_1)
1 0.0017 0.0281 0.0469 0.5235 ^ u2/Y (sky130_fd_sc_hd__nand2_1)
n2 (net)
0.0281 0.0000 0.5235 ^ ffc/D (sky130_fd_sc_hd__dfxtp_1)
0.5235 data arrival time
0.0000 0.0000 clock clk (rise edge)
0.0000 0.0000 clock source latency
1 0.0022 0.1000 0.0000 0.0000 ^ clk (in)
clk (net)
0.1000 0.0000 0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
2 0.0044 0.0334 0.1450 0.1450 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
cr (net)
0.0334 0.0000 0.1450 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
1 0.0019 0.0353 0.0724 0.2174 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
cc (net)
0.0353 0.0000 0.2174 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
-0.0138 0.2036 clock reconvergence pessimism
-0.0290 0.1746 library hold time
0.1746 data required time
-------------------------------------------------------------------------------------
0.1746 data required time
-0.5235 data arrival time
-------------------------------------------------------------------------------------
0.3489 slack (MET)Hold with ±5 % derates on the same tree. Early and late swap sides compared with setup.
The lesson L2.9 clock tree with ±5 % timing derates at the typical corner.
create_clock -name clk -period 1.0 [get_ports clk]
set_propagated_clock [all_clocks]
set_input_transition 0.1 [get_ports clk]
set_timing_derate -early 0.95
set_timing_derate -late 1.05
Prints: 0.5008 slack (MET) 0.3489 slack (MET)
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer says which paths are derated late and which early, for setup and for hold. It explains what CPPR (clock path pessimism removal) gives back.
What Interviewers Listen For (Senior)
A good senior answer compares flat derates with variation models that depend on path depth and distance. It asks where the derate numbers for the process come from.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItCompareScale It
- On-Chip Variation, Derates and CPPR
-
WhyThe Clock Reconvergence Pessimism LineL2 Mid-Level
What is the "clock reconvergence pessimism" line, and why was it zero in that report?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
With on-chip-variation derates, the launch clock is timed late and the capture clock early. Where the two clock paths share buffers, one buffer cannot be both. So the tool credits back the difference on the shared part. With no derates and a single corner, late equals early and the credit is zero. In lesson L2.9, ±5 % derates gave a credit of 0.0138 ns.
Timing pathSetup with ±5 % Derates and the CRPR Credit Whole pathffl → ffcsetup check, latest arrival3 cells
- Clock latency
- Cell delay
- Setup time
- Late launch clock
Through
rootandblwith the late derate: 0.2174 ns. - Early capture clock, then the credit
Through
rootandbcearly: 0.1967 ns. The CRPR line adds 0.0138 ns, the two speeds ofroot. - Slack
0.5008 ns. Without the credit it would be 0.4870 ns.
Read the path as a table
Launch: clk rise edge at 0.0000 ns, clock latency 0.2174 ns. Capture: clk rise edge at 1.0000 ns, latency 0.1967 ns, library setup time −0.1040 ns.
Arrival 0.6056 ns, required 1.1065 ns, slack 0.5008 ns (met).
Cell Arc Through Edge Delay (ns) Time (ns) Slew (ns) 1 ffl/CLK→ffl/Qdfxtp_1 fall 0.3094 0.5268 0.0345 ffl/Q→u1/Awire q1 fall 0.0000 0.5268 0.0345 2 u1/A→u1/Yinv_1 rise 0.0438 0.5706 0.0308 u1/Y→u2/Awire n1 rise 0.0000 0.5706 0.0308 3 u2/A→u2/Ynand2_1 fall 0.0350 0.6056 0.0251 u2/Y→ffc/Dwire n2 fall 0.0000 0.6056 0.0251 The report
Startpoint: ffl (rising edge-triggered flip-flop clocked by clk) Endpoint: ffc (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------------- 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock source latency 1 0.0022 0.1000 0.0000 0.0000 ^ clk (in) clk (net) 0.1000 0.0000 0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4) 2 0.0044 0.0334 0.1450 0.1450 ^ root/X (sky130_fd_sc_hd__clkbuf_4) cr (net) 0.0334 0.0000 0.1450 ^ bl/A (sky130_fd_sc_hd__clkbuf_1) 1 0.0019 0.0353 0.0724 0.2174 ^ bl/X (sky130_fd_sc_hd__clkbuf_1) cl (net) 0.0353 0.0000 0.2174 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1) 2 0.0044 0.0345 0.3094 0.5268 v ffl/Q (sky130_fd_sc_hd__dfxtp_1) q1 (net) 0.0345 0.0000 0.5268 v u1/A (sky130_fd_sc_hd__inv_1) 1 0.0024 0.0308 0.0438 0.5706 ^ u1/Y (sky130_fd_sc_hd__inv_1) n1 (net) 0.0308 0.0000 0.5706 ^ u2/A (sky130_fd_sc_hd__nand2_1) 1 0.0017 0.0251 0.0350 0.6056 v u2/Y (sky130_fd_sc_hd__nand2_1) n2 (net) 0.0251 0.0000 0.6056 v ffc/D (sky130_fd_sc_hd__dfxtp_1) 0.6056 data arrival time 1.0000 1.0000 clock clk (rise edge) 0.0000 1.0000 clock source latency 1 0.0022 0.1000 0.0000 1.0000 ^ clk (in) clk (net) 0.1000 0.0000 1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4) 2 0.0044 0.0334 0.1312 1.1312 ^ root/X (sky130_fd_sc_hd__clkbuf_4) cr (net) 0.0334 0.0000 1.1312 ^ bc/A (sky130_fd_sc_hd__clkbuf_1) 1 0.0019 0.0353 0.0655 1.1967 ^ bc/X (sky130_fd_sc_hd__clkbuf_1) cc (net) 0.0353 0.0000 1.1967 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1) 0.0138 1.2105 clock reconvergence pessimism -0.1040 1.1065 library setup time 1.1065 data required time ------------------------------------------------------------------------------------- 1.1065 data required time -0.6056 data arrival time ------------------------------------------------------------------------------------- 0.5008 slack (MET)Setup with ±5 % derates. The CRPR line gives back 0.0138 ns for the clock buffers both paths share.
Self-Check
Tick each key point you covered in your answer.
-
CompareFlat Derates vs Depth-Aware VariationL3 Senior
Compare a flat OCV derate with depth- and distance-aware or statistical variation models.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A flat derate applies the same percentage to every cell. That is pessimistic on deep paths, where random variation partly cancels, and can be optimistic on short ones. Depth- and distance-aware tables scale the derate with the number of stages and the spread of the path. Statistical models carry a sigma per cell arc and combine them along the path. All of them need data from the library; the method is only as good as that data.
Self-Check
Tick each key point you covered in your answer.
-
What IfCorners and Multi-Mode Multi-Corner AnalysisL1 JuniorL2 Mid-Level
What are timing corners and modes, and how would you choose which ones to sign off?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A corner is one process, voltage and temperature, with its own library. A mode is one set of constraints, such as functional or test. Sign-off times every required mode at every corner where some check could be worst: slow corners for setup, fast for hold. Both temperatures are needed, because which one is slower depends on the process. In the lesson the cold slow corner was worse than the hot one.
Timing pathThe Same Setup Path at the Slow CornerFlop ffllaunches,ffccaptures; both clocks come from oneclkbuf_4and their ownclkbuf_1. Libertysky130_fd_sc_hd__ss_n40C_1v60.Whole pathffl → ffcsetup check, latest arrival2 cells
- Clock latency
- Cell delay
- Setup time
- A slower clock
The clock reaches
fflafter 0.3654 ns, against 0.2071 ns at typical. - A slower path
Clock-to-Q and two gates: arrival 1.1566 ns, against 0.5768 ns.
- Violated
The flop's setup time grows too, to 0.3416 ns. Slack -0.1328 ns.
Read the path as a table
Launch: clk rise edge at 0.0000 ns, clock latency 0.3654 ns. Capture: clk rise edge at 1.0000 ns, latency 0.3654 ns, library setup time −0.3416 ns.
Arrival 1.1566 ns, required 1.0238 ns, slack −0.1328 ns (violated).
Cell Arc Through Edge Delay (ns) Time (ns) Slew (ns) 1 ffl/CLK→ffl/Qdfxtp_1 rise 0.6990 1.0644 0.1122 ffl/Q→u2/Bwire q1 rise 0.0000 1.0644 0.1122 2 u2/B→u2/Ynand2_1 fall 0.0921 1.1566 0.0374 u2/Y→ffc/Dwire n2 fall 0.0000 1.1566 0.0374 The report
Startpoint: ffl (rising edge-triggered flip-flop clocked by clk) Endpoint: ffc (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------------- 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock source latency 1 0.0021 0.1000 0.0000 0.0000 ^ clk (in) clk (net) 0.1000 0.0000 0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4) 2 0.0040 0.0573 0.2271 0.2271 ^ root/X (sky130_fd_sc_hd__clkbuf_4) cr (net) 0.0573 0.0000 0.2271 ^ bl/A (sky130_fd_sc_hd__clkbuf_1) 1 0.0016 0.0684 0.1383 0.3654 ^ bl/X (sky130_fd_sc_hd__clkbuf_1) cl (net) 0.0684 0.0000 0.3654 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1) 2 0.0044 0.1122 0.6990 1.0644 ^ ffl/Q (sky130_fd_sc_hd__dfxtp_1) q1 (net) 0.1122 0.0000 1.0644 ^ u2/B (sky130_fd_sc_hd__nand2_1) 1 0.0015 0.0374 0.0921 1.1566 v u2/Y (sky130_fd_sc_hd__nand2_1) n2 (net) 0.0374 0.0000 1.1566 v ffc/D (sky130_fd_sc_hd__dfxtp_1) 1.1566 data arrival time 1.0000 1.0000 clock clk (rise edge) 0.0000 1.0000 clock source latency 1 0.0021 0.1000 0.0000 1.0000 ^ clk (in) clk (net) 0.1000 0.0000 1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4) 2 0.0040 0.0573 0.2271 1.2271 ^ root/X (sky130_fd_sc_hd__clkbuf_4) cr (net) 0.0573 0.0000 1.2271 ^ bc/A (sky130_fd_sc_hd__clkbuf_1) 1 0.0016 0.0684 0.1383 1.3654 ^ bc/X (sky130_fd_sc_hd__clkbuf_1) cc (net) 0.0684 0.0000 1.3654 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1) 0.0000 1.3654 clock reconvergence pessimism -0.3416 1.0238 library setup time 1.0238 data required time ------------------------------------------------------------------------------------- 1.0238 data required time -1.1566 data arrival time ------------------------------------------------------------------------------------- -0.1328 slack (VIOLATED)The same setup path at the slow, cold corner fails by 0.1328 ns. At the typical corner it passes.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer defines a corner and a mode. It says setup is usually worst at the slow corner and hold at the fast one.
What Interviewers Listen For (Senior)
A good senior answer builds the table of modes and corners from the spec, and treats temperature inversion as something to measure. It drops a view only with evidence that another always dominates it. It adds RC corners.
Misconception
"The slow, hot corner is always the setup worst case."
At low voltage, cells can get slower when cold. In the lesson's clock tree the hot slow corner fails setup by 0.0059 ns and the cold slow corner by 0.1328 ns.
Run It
The lesson L2.9 clock tree at the slow, hot corner (100 °C, 1.60 V).
create_clock -name clk -period 1.0 [get_ports clk] set_propagated_clock [all_clocks] set_input_transition 0.1 [get_ports clk]Prints:
-0.0059 slack (VIOLATED)0.7329 slack (MET)See the Fix
create_clock -name clk -period 1.0 [get_ports clk] set_propagated_clock [all_clocks] set_input_transition 0.1 [get_ports clk]Prints:
-0.1328 slack (VIOLATED)0.7501 slack (MET)Half-Truth
"One typical corner with a margin is enough for sign-off."
A margin cannot capture hold at the fast corner or the temperature behaviour of the process. Each check must be met where it is worst.
Source ASIC Point lesson L7.1
-
WhyWhy the Cold Corner Can Be SlowerL2 Mid-Level
Why can a cold corner be slower than a hot one?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Temperature moves two things in opposite directions. Carrier mobility falls as it gets hotter, which slows cells. The threshold voltage also falls, which speeds them up. At low supply voltage, where the overdrive above threshold is small, the threshold effect can win, so cells are slower when cold. That is why the corner list includes both temperatures and the result is measured per library.
Timing pathSetup at ss_100C_1v60 ffl → ffcsetup check, latest arrival2 cells
- Clock latency
- Cell delay
- Setup time
Read the path as a table
Launch: clk rise edge at 0.0000 ns, clock latency 0.3593 ns. Capture: clk rise edge at 1.0000 ns, latency 0.3593 ns, library setup time −0.2659 ns.
Arrival 1.0993 ns, required 1.0934 ns, slack −0.0059 ns (violated).
Cell Arc Through Edge Delay (ns) Time (ns) Slew (ns) 1 ffl/CLK→ffl/Qdfxtp_1 rise 0.6394 0.9987 0.0971 ffl/Q→u2/Bwire q1 rise 0.0000 0.9987 0.0971 2 u2/B→u2/Ynand2_1 fall 0.1006 1.0993 0.0535 u2/Y→ffc/Dwire n2 fall 0.0000 1.0993 0.0535 The report
Startpoint: ffl (rising edge-triggered flip-flop clocked by clk) Endpoint: ffc (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: max Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------------- 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock source latency 1 0.0022 0.1000 0.0000 0.0000 ^ clk (in) clk (net) 0.1000 0.0000 0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4) 2 0.0042 0.0568 0.2295 0.2295 ^ root/X (sky130_fd_sc_hd__clkbuf_4) cr (net) 0.0568 0.0000 0.2295 ^ bl/A (sky130_fd_sc_hd__clkbuf_1) 1 0.0017 0.0560 0.1298 0.3593 ^ bl/X (sky130_fd_sc_hd__clkbuf_1) cl (net) 0.0560 0.0000 0.3593 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1) 2 0.0047 0.0971 0.6394 0.9987 ^ ffl/Q (sky130_fd_sc_hd__dfxtp_1) q1 (net) 0.0971 0.0000 0.9987 ^ u2/B (sky130_fd_sc_hd__nand2_1) 1 0.0016 0.0535 0.1006 1.0993 v u2/Y (sky130_fd_sc_hd__nand2_1) n2 (net) 0.0535 0.0000 1.0993 v ffc/D (sky130_fd_sc_hd__dfxtp_1) 1.0993 data arrival time 1.0000 1.0000 clock clk (rise edge) 0.0000 1.0000 clock source latency 1 0.0022 0.1000 0.0000 1.0000 ^ clk (in) clk (net) 0.1000 0.0000 1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4) 2 0.0042 0.0568 0.2295 1.2295 ^ root/X (sky130_fd_sc_hd__clkbuf_4) cr (net) 0.0568 0.0000 1.2295 ^ bc/A (sky130_fd_sc_hd__clkbuf_1) 1 0.0017 0.0560 0.1298 1.3593 ^ bc/X (sky130_fd_sc_hd__clkbuf_1) cc (net) 0.0560 0.0000 1.3593 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1) 0.0000 1.3593 clock reconvergence pessimism -0.2659 1.0934 library setup time 1.0934 data required time ------------------------------------------------------------------------------------- 1.0934 data required time -1.0993 data arrival time ------------------------------------------------------------------------------------- -0.0059 slack (VIOLATED)The same path at the slow, hot corner: -0.0059 ns. That is better than the cold corner's -0.1328 ns.
Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve L2.9.1: A Checker for Timing and Electrical LimitsSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
CompareWhich Corner Is Worst for Setup and for HoldL1 JuniorL2 Mid-Level
Compare the corners at which setup and hold are usually worst, and say why you check both everywhere.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Setup is usually worst where cells are slowest: a slow process at low voltage. Hold is usually worst where they are fastest: a fast process at high voltage. In the lesson's small clock tree the fast cold corner had the smallest hold slack, 0.2397 ns, and the slow corners failed setup. Skew and wire delays do not scale like cell delays, so sign-off still runs both checks at every corner.
Timing pathHold at ff_n40C_1v95 ffl → ffchold check, earliest arrival2 cells
- Clock latency
- Cell delay
- Hold time
Read the path as a table
Launch: clk rise edge at 0.0000 ns, clock latency 0.1420 ns. Capture: clk rise edge at 0.0000 ns, latency 0.1420 ns, library hold time −0.0167 ns.
Arrival 0.3650 ns, required 0.1253 ns, slack 0.2397 ns (met).
Cell Arc Through Edge Delay (ns) Time (ns) Slew (ns) 1 ffl/CLK→ffl/Qdfxtp_1 fall 0.1879 0.3300 0.0247 ffl/Q→u2/Bwire q1 fall 0.0000 0.3300 0.0247 2 u2/B→u2/Ynand2_1 rise 0.0351 0.3650 0.0210 u2/Y→ffc/Dwire n2 rise 0.0000 0.3650 0.0210 The report
Startpoint: ffl (rising edge-triggered flip-flop clocked by clk) Endpoint: ffc (rising edge-triggered flip-flop clocked by clk) Path Group: clk Path Type: min Fanout Cap Slew Delay Time Description ------------------------------------------------------------------------------------- 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock source latency 1 0.0023 0.1000 0.0000 0.0000 ^ clk (in) clk (net) 0.1000 0.0000 0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4) 2 0.0045 0.0251 0.0966 0.0966 ^ root/X (sky130_fd_sc_hd__clkbuf_4) cr (net) 0.0251 0.0000 0.0966 ^ bl/A (sky130_fd_sc_hd__clkbuf_1) 1 0.0019 0.0260 0.0454 0.1420 ^ bl/X (sky130_fd_sc_hd__clkbuf_1) cl (net) 0.0260 0.0000 0.1420 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1) 2 0.0044 0.0247 0.1879 0.3300 v ffl/Q (sky130_fd_sc_hd__dfxtp_1) q1 (net) 0.0247 0.0000 0.3300 v u2/B (sky130_fd_sc_hd__nand2_1) 1 0.0017 0.0210 0.0351 0.3650 ^ u2/Y (sky130_fd_sc_hd__nand2_1) n2 (net) 0.0210 0.0000 0.3650 ^ ffc/D (sky130_fd_sc_hd__dfxtp_1) 0.3650 data arrival time 0.0000 0.0000 clock clk (rise edge) 0.0000 0.0000 clock source latency 1 0.0023 0.1000 0.0000 0.0000 ^ clk (in) clk (net) 0.1000 0.0000 0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4) 2 0.0045 0.0251 0.0966 0.0966 ^ root/X (sky130_fd_sc_hd__clkbuf_4) cr (net) 0.0251 0.0000 0.0966 ^ bc/A (sky130_fd_sc_hd__clkbuf_1) 1 0.0019 0.0260 0.0454 0.1420 ^ bc/X (sky130_fd_sc_hd__clkbuf_1) cc (net) 0.0260 0.0000 0.1420 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1) 0.0000 0.1420 clock reconvergence pessimism -0.0167 0.1253 library hold time 0.1253 data required time ------------------------------------------------------------------------------------- 0.1253 data required time -0.3650 data arrival time ------------------------------------------------------------------------------------- 0.2397 slack (MET)Hold at the fast, cold corner: 0.2397 ns, the smallest hold slack of the three corners.
create_clock -name clk -period 1.0 [get_ports clk] set_propagated_clock [all_clocks] set_input_transition 0.1 [get_ports clk]Prints:
0.6973 slack (MET)0.2397 slack (MET)Self-Check
Tick each key point you covered in your answer.
-
Scale ItPruning the Mode and Corner MatrixL3 SeniorL4 Staff
Your chip has five modes and twelve corners. How do you keep sign-off affordable without missing the worst case?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
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Reveal the Model Answer
Start from the full matrix, and drop a view only with evidence that another view always dominates it. Get that evidence by running everything once on an early netlist, for example. Keep every view that is worst for some endpoint group in any check. Optimise on a small set of dominant views, but run the full set at sign-off and after every late change.
Self-Check
Tick each key point you covered in your answer.
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What IfHold Repair Across Four CornersL2 Mid-LevelL3 Senior
Your hold repair passes at the fast corner but fails setup at the slow corner. How do you close both?
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Reveal the Model Answer
Repair against all required corners at once. Then the tool sees the setup cost at the slow corner when it inserts delay at the fast one. Prefer delay on paths with setup slack to spare at every corner. Fix shared skew in the clock tree before adding cells. A repair that must break setup to fix hold shows the constraints or the clock tree need work, not more cells.
Self-Check
Tick each key point you covered in your answer.
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Prove ItSolve L7.1.1: Make the Hold Repair Survive Four CornersSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Break ItOne Delay Cell for Forty Hold FixesL2 Mid-LevelL3 Senior
Break it: the repair fixes forty hold violations with one delay cell on a shared net. What can go wrong?
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Reveal the Model Answer
The shared net also feeds long paths, and they slow down by the same delay. With tight setup at the slow corner, those paths now fail. Put the delay near each failing D pin instead, where only the short path passes. Then check setup at every corner again.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"One cell for forty fixes is always the best repair."
It is the cheapest in area, but its delay lands on every path through that net. Paths with no setup margin then fail.
Source Lesson L5.5 key points
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Prove ItSolve L2.9.1: A Checker for Timing and Electrical LimitsSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Half-Truth
"Derate everything by 5 % and you are covered."
A flat number is a guess. Variation per cell shrinks along a deep path as random effects average out. The foundry or library supplies the real data. The lesson calls its ±5 % illustrative.
Source ASIC Point lesson L2.9 (no public SKY130 OCV derate found; ±5 % illustrative)
Misconception
"CPPR is extra margin the tool adds."
It is margin the tool removes: the derates double-count variation on the shared clock segment, and CPPR subtracts that double count.
Source ASIC Point lesson L2.9 (CRPR 0.0138 ns measured)
Buzzword Without Mechanism
Names AOCV and POCV but cannot say what changes.
The point is that the derate depends on path depth and distance, or on a statistical sigma per cell. It is not one flat number.