Setup and Hold Checks

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItCompareScale It

1. Setup and Hold Checks
2. WhyWhy the Period Cancels in HoldL0 FresherL1 Junior

   Explain, edge by edge, why the hold check does not depend on the clock period.

   Reveal the Model Answer

   At one clock edge the launch flop sends new data and the capture flop samples old data. Hold asks whether the new data reaches the capture flop before its hold window around that same edge closes. Both events come from the same edge, so the period is not in the inequality at all. Setup is different: it compares this edge with the next one.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 At one clock edge the launch flop sends new data and the capture flop samples old data. Key point 2 Hold asks whether the new data reaches the capture flop before its hold window around that same edge closes. Key point 3 Both events come from the same edge, so the period is not in the inequality at all. Key point 4 Setup is different: it compares this edge with the next one.

   • Lesson L2.4Setup and Hold with Skew and Uncertainty
3. What IfSlowing the Clock to Fix a FailureL1 Junior

   What if a chip fails on the bench? Does lowering the clock frequency tell you whether it is setup or hold?

   Reveal the Model Answer

   Yes, because hold does not depend on the period. A setup failure goes away at a lower frequency. A hold failure stays at any frequency. It needs a fix to the short path or the skew.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Yes, because hold does not depend on the period. Key point 2 A setup failure goes away at a lower frequency. Key point 3 A hold failure stays at any frequency. Key point 4 It needs a fix to the short path or the skew.

   Misconception

   "Slow the clock until the hold failure passes."

   That fixes setup only. Hold compares two events from the same edge, so the period never enters it.

   Source Lesson L2.4 key points

   • Lesson L2.4Setup and Hold with Skew and Uncertainty
4. What IfWhat Skew Does to Setup and HoldL1 JuniorL2 Mid-Level

   Asked if they mention clock skew

   The capture flop's clock arrives 0.3 ns after the launch flop's. What happens to setup and hold slack?

   Reveal the Model Answer

   Positive skew, capture later than launch, gives setup that much more time and takes the same amount from hold. In lesson L2.4 each extra buffer in front of the capture flop's clock raised setup slack by about 0.073 ns. Hold slack fell by the same amount, until hold failed at the fifth buffer.

   • setup slack
   • hold slack

   1. Capture-clock buffers 0setup slack = 606.7 ps · hold slack = 333.4 ps

      No skew: setup slack 0.6067 ns, hold slack 0.3334 ns. The flop's own clock-to-Q protects hold.

   2. Capture-clock buffers 4setup slack = 900 ps · hold slack = 33.5 ps

      4 buffers: hold slack 0.0335 ns, still met.

   3. Capture-clock buffers 5setup slack = 973.4 ps · hold slack = -39.9 ps

      5 buffers: hold slack -0.0399 ns. Setup has grown to 0.9734 ns, and a slower clock would add only to that.

   Read the plot as a table

   Capture-clock buffers	setup slack	hold slack
   0	606.7 ps	333.4 ps
   1	679.8 ps	253.8 ps
   2	753.3 ps	180.2 ps
   3	826.6 ps	106.9 ps
   4	900 ps	33.5 ps
   5	973.4 ps	-39.9 ps
   6	1.047 ns	-113.3 ps
   7	1.12 ns	-186.6 ps

   Each buffer added to the capture clock raises setup slack and lowers hold slack by the same step. Hold fails at the fifth buffer.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Positive skew, capture later than launch, gives setup that much more time and takes the same amount from hold. Key point 2 In lesson L2.4 each extra buffer in front of the capture flop's clock raised setup slack by about 0.073 ns. Key point 3 Hold slack fell by the same amount, until hold failed at the fifth buffer.

   • Lesson L2.4Setup and Hold with Skew and Uncertainty
   • Lesson L5.1Skew, Latency and Insertion Delay
   • Problem L2.4.1The Smallest Hold Repair
5. Prove ItSolve L2.4.1: The Smallest Hold RepairSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L2.4.1

6. CompareWhich Corner Is Worst for Setup and for HoldL1 JuniorL2 Mid-Level

   Compare the corners at which setup and hold are usually worst, and say why you check both everywhere.

   Reveal the Model Answer

   Setup is usually worst where cells are slowest: a slow process at low voltage. Hold is usually worst where they are fastest: a fast process at high voltage. In the lesson's small clock tree the fast cold corner had the smallest hold slack, 0.2397 ns, and the slow corners failed setup. Skew and wire delays do not scale like cell delays, so sign-off still runs both checks at every corner.

   ffl → ffchold check, earliest arrival2 cells

   • Clock latency
   • Cell delay
   • Hold time

   Read the path as a table

   Launch: clk rise edge at 0.0000 ns, clock latency 0.1420 ns. Capture: clk rise edge at 0.0000 ns, latency 0.1420 ns, library hold time −0.0167 ns.

   Arrival 0.3650 ns, required 0.1253 ns, slack 0.2397 ns (met).

   Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
   1	ffl/CLK → ffl/Q	dfxtp_1	fall	0.1879	0.3300	0.0247
   	ffl/Q → u2/B	wire q1	fall	0.0000	0.3300	0.0247
   2	u2/B → u2/Y	nand2_1	rise	0.0351	0.3650	0.0210
   	u2/Y → ffc/D	wire n2	rise	0.0000	0.3650	0.0210

   The report

   Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
   Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
   Path Group: clk
   Path Type: min
   
   Fanout       Cap      Slew     Delay      Time   Description
   -------------------------------------------------------------------------------------
                                 0.0000    0.0000   clock clk (rise edge)
                                 0.0000    0.0000   clock source latency
        1    0.0023    0.1000    0.0000    0.0000 ^ clk (in)
                                                    clk (net)
                       0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
        2    0.0045    0.0251    0.0966    0.0966 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                    cr (net)
                       0.0251    0.0000    0.0966 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
        1    0.0019    0.0260    0.0454    0.1420 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
                                                    cl (net)
                       0.0260    0.0000    0.1420 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
        2    0.0044    0.0247    0.1879    0.3300 v ffl/Q (sky130_fd_sc_hd__dfxtp_1)
                                                    q1 (net)
                       0.0247    0.0000    0.3300 v u2/B (sky130_fd_sc_hd__nand2_1)
        1    0.0017    0.0210    0.0351    0.3650 ^ u2/Y (sky130_fd_sc_hd__nand2_1)
                                                    n2 (net)
                       0.0210    0.0000    0.3650 ^ ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                           0.3650   data arrival time
   
                                 0.0000    0.0000   clock clk (rise edge)
                                 0.0000    0.0000   clock source latency
        1    0.0023    0.1000    0.0000    0.0000 ^ clk (in)
                                                    clk (net)
                       0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
        2    0.0045    0.0251    0.0966    0.0966 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                    cr (net)
                       0.0251    0.0000    0.0966 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
        1    0.0019    0.0260    0.0454    0.1420 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
                                                    cc (net)
                       0.0260    0.0000    0.1420 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                                 0.0000    0.1420   clock reconvergence pessimism
                                -0.0167    0.1253   library hold time
                                           0.1253   data required time
   -------------------------------------------------------------------------------------
                                           0.1253   data required time
                                          -0.3650   data arrival time
   -------------------------------------------------------------------------------------
                                           0.2397   slack (MET)

   Hold at the fast, cold corner: 0.2397 ns, the smallest hold slack of the three corners.

   create_clock -name clk -period 1.0 [get_ports clk]
   set_propagated_clock [all_clocks]
   set_input_transition 0.1 [get_ports clk]
   

   Prints: 0.6973 slack (MET) 0.2397 slack (MET)

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Setup is usually worst where cells are slowest: a slow process at low voltage. Key point 2 Hold is usually worst where they are fastest: a fast process at high voltage. Key point 3 In the lesson's small clock tree the fast cold corner had the smallest hold slack, 0.2397 ns, and the slow corners failed setup. Key point 4 Skew and wire delays do not scale like cell delays, so sign-off still runs both checks at every corner.

   • Lesson L2.9Corners, Derates, OCV and CPPR
   • Lesson L7.1Sign-Off Timing: Every Corner, Every Check
7. Scale ItPruning the Mode and Corner MatrixL3 SeniorL4 Staff

   Your chip has five modes and twelve corners. How do you keep sign-off affordable without missing the worst case?

   Reveal the Model Answer

   Start from the full matrix, and drop a view only with evidence that another view always dominates it. Get that evidence by running everything once on an early netlist, for example. Keep every view that is worst for some endpoint group in any check. Optimise on a small set of dominant views, but run the full set at sign-off and after every late change.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Start from the full matrix, and drop a view only with evidence that another view always dominates it. Key point 2 Get that evidence by running everything once on an early netlist, for example. Key point 3 Keep every view that is worst for some endpoint group in any check. Key point 4 Optimise on a small set of dominant views, but run the full set at sign-off and after every late change.

   • Lesson L7.1Sign-Off Timing: Every Corner, Every Check
   • Lesson L7.6The Sign-Off Review