Interview Question · Waveform
AHB Wait States, HREADY and HREADYOUT
The Question
The interviewer asks
A subordinate inserts two wait states on a read. What happens on the bus during those cycles? And what is the difference between HREADY and HREADYOUT?
Rising edge 0 1 2 3
Address phase READ A next held held
Data phase prior READ A READ A READ A
HREADY 1 0 0 1
HRDATA - ? ? D[A]
Annotate the address/control signals that must remain stable.You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The wait states stretch the data phase of the read. They also stretch the address phase of the next transfer, which stays on the wires until HREADY is high. Each subordinate drives HREADYOUT for its own data phase. The multiplexor picks the HREADYOUT of the subordinate whose data phase is active. It sends that as HREADY to the manager and to every subordinate. A subordinate takes an address phase only at an edge where its HSEL and HREADY are both high.
xfer is HTRANS[1], 1 for NONSEQ or SEQ.A token flies when an address phase is accepted: a transfer on HTRANS and HREADY high.
- Cycle 1
A's address phase, 0x1000, is accepted: NONSEQ and
HREADYhigh. - Cycle 2
A's data phase starts with 11 on
HWDATA, and B's address 0x1010 is already on the wires. The memory drivesHREADYOUTlow: nothing is accepted at this edge. - Cycle 3
Still waiting. The manager holds both the data of A and the address of B exactly as they were.
- Cycle 4
HREADYis high: A's data is written and B's address is accepted at the same edge. - Cycle 5
B's data, 22, moves while the read of 0x1000 is in its address phase. No waits this time.
- Cycle 6
The read's data phase ends with 11 on
HRDATA, the word A wrote.
A wait state costs every transfer in the pipeline a cycle, not only the slow one.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says the next address phase is held during the wait. It tells HREADYOUT, one per subordinate, apart from HREADY, the shared bus signal.
What Interviewers Listen For (Mid-Level)
A good mid-level answer knows what a manager may still change in a wait. Those are an IDLE's address, IDLE to NONSEQ, and BUSY to SEQ. It explains why a subordinate needs HREADY as an input.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItScale It
- AHB Wait States, HREADY and HREADYOUT
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WhyWhy a Subordinate Takes HREADY InL1 JuniorL2 Mid-Level
A subordinate drives HREADYOUT. Why does it also need the bus HREADY as an input?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The data phase in front may belong to another subordinate. HREADY says when that data phase ends. Only then does the address phase on the wires count as accepted. A subordinate that samples on HSEL alone may act too early. The address phase may still change, such as an IDLE becoming NONSEQ, or the manager may cancel it after an ERROR.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says HREADY tells the subordinate that the transfer in front has finished.
What Interviewers Listen For (Mid-Level)
A good mid-level answer gives the failure. If another data phase is stretched, a subordinate that looks only at HSEL takes the same address phase several times. Or it takes one that later changes.
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Break ItA Subordinate That Samples on HSEL AloneL2 Mid-Level
Break it: a subordinate takes address and control whenever HSEL is high and ignores HREADY. Show the failure.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
While the data phase in front is in a wait state, HSEL and the address can already point at this subordinate. It then takes a transfer the bus has not accepted yet. If the manager changes IDLE to NONSEQ, or cancels after an ERROR, the subordinate acts on the wrong transfer. Across a long wait it can even take one transfer twice.
Self-Check
Tick each key point you covered in your answer.
Spec Misquote
"HSEL is high, so the transfer is for me and I take it."
HSEL only says the address decodes to you. The address phase counts only in a cycle where HREADY is high.
Source AMBA AHB Protocol Specification IHI 0033C §4.2 Address decoding
-
What IfHTRANS During a Wait StateL2 Mid-Level
While HREADY is low, may the manager change HTRANS? Give the exceptions.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Normally no, with three exceptions. IDLE may become NONSEQ, and in a fixed-length burst BUSY may become SEQ. In an undefined-length INCR burst, BUSY may become anything, and IDLE or NONSEQ ends the burst. After any such change, HTRANS is held until HREADY is high. The address may change only for IDLE, or after an ERROR has started.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer lists the three exceptions where HTRANS may change in a wait. It says HTRANS then holds until HREADY is high.
What Interviewers Listen For (Senior)
A good senior answer writes the hold checker with each exception as its own OR term. It makes stimulus hit each exception, so the checker does not pass without testing anything.
-
Prove ItSolve P4.4.1: The Hold CheckerSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
Scale ItBounding AHB Wait StatesL3 Senior
Why should every AHB subordinate have a known maximum number of wait states? How would you check that across an SoC?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Wait states stall the whole AHB interface. So the worst-case latency of every manager depends on the slowest subordinate it can reach. A known maximum per subordinate lets you compute that latency. Check it with a watchdog per subordinate, set to its documented bound. Add performance tests that hit the worst case and, for small blocks, a bounded-response property in formal.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer explains that a wait state stalls the whole bus. It turns each subordinate's documented maximum wait into a checked parameter.
What Interviewers Listen For (Staff)
A good staff answer adds the system view: in a multi-layer interconnect, arbitration delay adds to each subordinate's bound. It sets a latency budget for each real-time manager.
-
Break ItRules for an AHB MonitorL2 Mid-LevelL3 Senior
Write down the rules your AHB monitor uses. When is an address phase taken, and when does its data phase end? What do monitors usually get wrong?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
An address phase is taken at an edge where HREADY is high and HTRANS is NONSEQ or SEQ. On a subordinate port, HSEL must be high too. Its data phase ends at the next edge where HREADY is high, and HWDATA, HRDATA and HRESP belong to it there. Monitors often log at the address phase and pair the wrong data. Others ignore HREADY and log a waiting transfer several times, or read HRESP as final in the first ERROR cycle.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer names both edges correctly: where the address phase is taken and where its data phase ends. It keeps one pending transfer between them.
What Interviewers Listen For (Senior)
A good senior answer handles the ERROR case, where the next address phase may be cancelled to IDLE. It keeps the monitor passive and the checks separate, and adds coverage on HBURST, HSIZE, waits and BUSY.
-
Prove ItSolve P4.11.1: The AHB MonitorSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
Prove ItSolve P4.4.1: The Hold CheckerSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.
Missed Corner
A monitor can count a transfer at every edge where HTRANS is NONSEQ or SEQ.
While a data phase is stretched, the next transfer waits on the wires and shows NONSEQ at every edge. Below, the naive monitor logs 0x24 three times. Only edges with HREADY high count.
Run It
t=15 naive monitor logs address 0x00000020 t=15 HREADY monitor logs address 0x00000020 t=25 naive monitor logs address 0x00000024 t=35 naive monitor logs address 0x00000024 t=45 naive monitor logs address 0x00000024 t=45 HREADY monitor logs address 0x00000024 FAIL naive monitor counted 4 address phases; the bus carried 2 PASS HREADY monitor counted 2 address phases; the bus carried 2Spec Misquote
The manager may change the address freely during a wait state.
It may change only while the waiting address phase is IDLE, or after an ERROR has started. Once it shows NONSEQ or SEQ, the address is held until HREADY is high.
Source AMBA AHB Protocol Specification IHI 0033C §3.7.2 Address changes during wait states
Misconception
A subordinate only needs HSELx; HREADY is the manager's business.
A selected subordinate must also see HREADY high. That tells it the previous transfer has finished, even if it belonged to another subordinate. Sampling on HSEL alone takes transfers that have not been accepted.
Source AMBA AHB Protocol Specification IHI 0033C §2.4 Decoder signals; §4.2 Address decoding