Byte Lanes and WSTRB for Narrow Transfers

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItScale It

1. Byte Lanes and WSTRB for Narrow Transfers
2. WhyByte Invariance and EndiannessL2 Mid-Level

   A big-endian core and a little-endian core share an AXI memory. Does AXI swap bytes for one of them?

   Reveal the Model Answer

   No. AXI is byte invariant: the byte at address word+n always travels on lane n, whichever core sent it. Endianness only decides which byte of a multi-byte value goes to which address, inside each core. So the bus never swaps lanes. A core that wants the other's view of a 32-bit value reverses the bytes in software or in its own interface.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 No. Key point 2 AXI is byte invariant: the byte at address word+n always travels on lane n, whichever core sent it. Key point 3 Endianness only decides which byte of a multi-byte value goes to which address, inside each core. Key point 4 So the bus never swaps lanes. Key point 5 A core that wants the other's view of a 32-bit value reverses the bytes in software or in its own interface.
3. What IfA Bridge That Swaps Byte LanesL2 Mid-LevelL3 Senior

   What if a bridge designer swaps byte lanes on one path to fix endianness for the big-endian core?

   Reveal the Model Answer

   Then byte invariance breaks on that path. A single byte written to word+1 now lands at word+2. Byte-wide software breaks, and the other core reads scrambled data. Endianness belongs inside each core, never on the bus.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Then byte invariance breaks on that path. Key point 2 A single byte written to word+1 now lands at word+2. Key point 3 Byte-wide software breaks, and the other core reads scrambled data. Key point 4 Endianness belongs inside each core, never on the bus.

   Misconception

   "Swapping lanes in the interconnect turns big-endian into little-endian."

   It swaps every access, including single bytes, which have no endianness. Byte addresses then point at the wrong data.

   Source AMBA AXI Protocol Specification IHI 0022L §A3.2.4 Byte invariance

   • Lesson P2.7Narrow Transfers, Byte Lanes and Width Conversion
4. What IfStrobes Outside the TransferL1 JuniorL2 Mid-Level

   A 1-byte write to 0x1001 arrives with WSTRB 0110. Legal? And a beat with WSTRB 0000?

   Reveal the Model Answer

   WSTRB 0110 is illegal. The beat addresses only lane 1, so the lane 2 strobe lies outside the transfer and must be low. WSTRB 0000 is legal: inside the beat's lanes any pattern is allowed, including none, and that beat writes nothing. A manager uses all-zero strobes to finish a burst it no longer needs, because a burst cannot end early.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 WSTRB 0110 is illegal. Key point 2 The beat addresses only lane 1, so the lane 2 strobe lies outside the transfer and must be low. Key point 3 WSTRB 0000 is legal: inside the beat's lanes any pattern is allowed, including none, and that beat writes nothing. Key point 4 A manager uses all-zero strobes to finish a burst it no longer needs, because a burst cannot end early.
5. Break ItRight Strobes, Wrong LanesL2 Mid-LevelL3 Senior

   A DMA streams 16-bit samples with perfect strobes, and every second sample is lost. The protocol checker is silent. What happened?

   Illustrative DMA debug excerpt
   Source samples: 1122, 3344, 5566, 7788
   Destination:    1122, 0000, 5566, 0000
   AXI protocol errors: 0
   WSTRB matches each addressed halfword.

   Reveal the Model Answer

   The data stayed in lanes 0 and 1, while the strobes moved to lanes 2 and 3 for the odd addresses. The strobes alone are legal, so no protocol rule fires. The subordinate writes whatever sits in the strobed lanes. Only a data check catches it: a scoreboard or read-back that compares bytes by address. Lesson P2.7 measured the result: 11 11 00 00 33 33 00 00.

   A lit cell is a byte the memory wrote in that beat.

   1. Cycle 0

      The request: four transfers of two bytes from 0x3000, an INCR burst.

   2. Cycle 1

      Beat 0 is for 0x3000: lanes 0 and 1, strobe 0011, sample 1111 in the low half. Correct.

   3. Cycle 2

      Beat 1 is for 0x3002: lanes 2 and 3, strobe 1100. The engine left 2222 in the low half, so lanes 2 and 3 carry zeros, and the memory writes the zeros.

   4. Cycle 3

      Beat 2 is back in the low lanes, so 3333 lands where it should.

   5. Cycle 4

      Beat 3 repeats the mistake at 0x3006. The strobes were legal on every beat; the data was in the wrong place on two of them.

   Measured: the buffer reads 11 11 00 00 33 33 00 00 afterwards. The protocol checker reports no broken rule.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The data stayed in lanes 0 and 1, while the strobes moved to lanes 2 and 3 for the odd addresses. Key point 2 The strobes alone are legal, so no protocol rule fires. Key point 3 The subordinate writes whatever sits in the strobed lanes. Key point 4 Only a data check catches it: a scoreboard or read-back that compares bytes by address. Key point 5 Lesson P2.7 measured the result: 11 11 00 00 33 33 00 00.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer names the bug: right strobes, data in the wrong lanes. It says only a check on the data can see it.

   • Lesson P2.7Narrow Transfers, Byte Lanes and Width Conversion
   • Problem P2.7.1The Lane Mapper
   • Problem P2.18.4The Beat That Landed in the Wrong Word
6. Scale ItUpsizers, Downsizers and ModifiableL3 Senior

   You put a 32-to-64-bit upsizer and a 64-to-32-bit downsizer in a fabric. Which transactions are they allowed to reshape?

   Reveal the Model Answer

   A Non-modifiable transaction (AxCACHE[1] low) must not be split or merged. It keeps its address, size, length and burst type. So an upsizer steers each narrow beat into the right half of the wide word and leaves size and length alone. It may pack beats only when the transaction is Modifiable. A downsizer must split anyway when Size exceeds the narrow bus, a case the spec admits cannot meet the rule.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A Non-modifiable transaction (AxCACHE[1] low) must not be split or merged. Key point 2 It keeps its address, size, length and burst type. Key point 3 So an upsizer steers each narrow beat into the right half of the wide word and leaves size and length alone. Key point 4 It may pack beats only when the transaction is Modifiable. Key point 5 A downsizer must split anyway when Size exceeds the narrow bus, a case the spec admits cannot meet the rule.

   What Interviewers Listen For (Senior)

   A good senior answer ties packing beats to AxCACHE[1], the Modifiable bit. It knows the downsizing exception, and that split responses must be joined back together.

7. Prove ItSolve P2.7.1: The Lane MapperSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem P2.7.1