Interview Question · Concept
Why I2C Is Open Drain
- Likely at Google
The Question
The interviewer asks
I2C outputs are open drain with pull-up resistors. Why not ordinary push-pull outputs, and what does that choice cost?
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Reveal the Model Answer
Each device can only pull a line low or let go. A pull-up resistor raises the line when every device lets go. So the line is the wired-AND of all devices, and two drivers never fight. That makes clock stretching, clock synchronisation and multi-controller arbitration possible. It also lets parts on different supplies share a bus. The cost is the rising edge: a resistor charges the bus capacitance, which limits speed and bus size.
A low lane of 1 pulls the net down. The pull-up raises it only when every device releases.
- Cycle 0
Both devices let go. The pull-up resistor holds SDA high: the idle bus.
- Cycle 1
The controller pulls. One pull is enough: SDA is low.
- Cycle 2
Both pull. Nothing fights; the line is simply low.
- Cycle 3
The controller lets go, but the target still pulls. SDA stays low, and the controller can see it by reading the pin.
- Cycle 4
The target lets go too. Only now does the resistor pull SDA back up.
SDA is high only when every device has let go: a wired-AND. Clock stretching and arbitration both come from this one property.
A low lane of 1 pulls the net down. The pull-up raises it only when every device releases.
Read phases and sample points (quarter bit)
- START: columns 2 through 3.
- 0xa0 + ACK: columns 4 through 39.
- 0x3c + ACK: columns 40 through 75.
- STOP: columns 76 through 79.
- SDA sampled at 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62, 66, 70, 74.
- Cycle 1
START: the controller pulls SDA while SCL is high.
- Cycle 6
Address bits: the controller pulls for every 0 and lets go for every 1. The target only listens.
- Cycle 38
The ninth clock:
ctrl_lowis 0 andtgt_lowis 1. The target pulls SDA to acknowledge. - Cycle 74
The data byte has its own ninth clock, and the target pulls again.
- Cycle 78
STOP: the controller lets SDA rise while SCL is high.
Generated from the transaction and decoded back from SCL and SDA. Dots mark where SDA is sampled, once per SCL high.
Falling edge
A transistor discharges the line: fast.
Rising edge
Rp charges Cb: 0.3 to 0.7 VDD takes 0.8473 Rp × Cb (UM10204 §7.1).
What the AND buys
A target can hold SCL low (stretching); a controller that sends 1 and sees 0 knows it lost (arbitration).
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Fresher)
A good fresher answer says no device ever drives a 1, so the line is high only when every device lets go. It names at least one feature that needs this, such as clock stretching or arbitration.
What Interviewers Listen For (Junior)
A good junior answer explains why push-pull outputs would short together during arbitration or an ACK. It says the rise time, not the protocol, sets the speed limit.
What Interviewers Listen For (Mid-Level)
A good mid-level answer puts a number on the rise: 0.8473 RC between the two thresholds. It knows a bus with one controller and no stretching target may use a push-pull SCL (UM10204 section 3.1.1).
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyProve ItBreak ItCompareScale It
- Why I2C Is Open Drain
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WhyA Push-Pull Device on SDAL0 FresherL1 Junior
A new target drives SDA high actively whenever it is not pulling low. What happens on the bus?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The first time another device pulls SDA low while this one drives high, two outputs fight. In simulation the line resolves to x. On a board, the two transistors set a voltage, often between VIL and VIH, so receivers disagree. ACKs, arbitration and the controller's own bits all break. The fight can also damage drivers.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Fresher)
A good fresher answer says it is a short between a device driving high and one driving low. The bus value becomes undefined.
What Interviewers Listen For (Junior)
A good junior answer points to when it happens: the controller's address bits and the other side's ACK. It knows a checker that sees who pulls finds it, and a checker on the wire alone cannot.
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CompareSizing the I2C Pull-UpL1 JuniorL2 Mid-Level
You have a Fast-mode bus at 3.3 V with about 100 pF. How do you choose the pull-up resistor?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Two bounds. Rp(max) comes from the rise-time limit: tr = 0.8473 Rp Cb. With 300 ns and 100 pF, Rp is at most about 3.5 kΩ. Rp(min) comes from the sink current: (VDD − 0.4 V) / 3 mA, about 967 Ω. Pick inside that window, toward the high end if supply current matters. At 400 pF in Fast-mode the window is empty, so a resistor alone cannot work.
TransientThree Pull-Ups into 400 pFThe maximum Sm/Fm bus load. - 1 kΩ
- 2.2 kΩ
- 4.7 kΩ
Read the plot as a table
Time 1 kΩ 2.2 kΩ 4.7 kΩ 500 ns 2.355 V 1.43 V 770.6 mV 1 µs 3.029 V 2.241 V 1.361 V 1.5 µs 3.222 V 2.7 V 1.814 V 2 µs 3.278 V 2.96 V 2.161 V 2.5 µs 3.294 V 3.107 V 2.427 V 3 µs 3.298 V 3.191 V 2.631 V Simulated on the Analog engine (ngspice 42) at 3.3 V into 400 pF. Read each rise time between the 0.3 VDD and 0.7 VDD lines.
Mode Cb Rp(min) Rp(max) Window Fm 100 pF 967 Ω (3 mA) 3.54 kΩ (300 ns) 967 Ω to 3.54 kΩ Fm 400 pF 967 Ω (3 mA) 885 Ω (300 ns) empty Fm+ 550 pF 145 Ω (20 mA) 258 Ω (120 ns) 145 Ω to 258 Ω Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer knows the pull-up has two limits. The maximum rise time sets the largest resistor, and the sink current at VOL sets the smallest.
What Interviewers Listen For (Mid-Level)
A good mid-level answer works out the window and notices it can be empty at Fast-mode with 400 pF. It names the fixes: a current-source or switched pull-up, Fm+ drivers, or a slower clock.
-
Scale ItAn 800 pF I2C BusL2 Mid-LevelL3 Senior
The sensor cable makes your bus 800 pF, twice the Fast-mode limit. What are your options, and what does each cost?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
UM10204 lists four options. Run a slower SCL so the rise fits, or use higher-drive parts, such as Fm+ devices, with a stronger pull-up. Split the bus with buffers, multiplexers or switches so each segment stays under the limit, or add a switched pull-up. Buffers add delay to every edge and may bring their own VIL/VOL rules. Fm+ still stops at 550 pF and 1 MHz.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer names at least three of the four options. It knows a buffer splits the bus capacitance into segments.
What Interviewers Listen For (Senior)
A good senior answer weighs them. Buffers add delay, and Fm+ needs every part on the segment to sink 20 mA. It adds wire flight time to the budget for very long buses.
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Break ItWhat a Digital I2C Checker Cannot SeeL2 Mid-Level
Your I2C timing checker in simulation is clean. Does that prove the bus meets UM10204 timing?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
No. A digital checker measures edge-to-edge times such as tLOW, tHIGH, tSU;DAT and tBUF on 0/1 pins. Rise time, fall time, spike width and bus capacitance are analog. In RTL the pins switch instantly, so a pull-up that is far too weak still passes. Those rows need SPICE or a board measurement, plus the pull-up arithmetic.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer splits the timing table into what a logic simulator can measure and what it cannot. It names an analog check, such as SPICE or a board measurement, for the rest.
Tool as Truth
"The waveform shows sharp edges, so tr is fine."
An RTL model has no capacitance. The sharp edge comes from the simulator, not the bus. On a board, a 4.7 kΩ pull-up on 400 pF rises in about 1.6 µs. In RTL, it still looks instant.
Source NXP UM10204 rev. 7 §7.1 (0.8473 RC); Lesson P8.7 SPICE table
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Prove ItSolve P8.1.1: Read the Open-Drain Driver ViewSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Buzzword Without Mechanism
"Open drain is for low power."
Power is not the reason, because a low line burns current through the pull-up. The reason is the wired-AND: any device may pull, and none may fight. Stretching and arbitration need that.
Spec Misquote
"Both lines must always be open drain, no exceptions."
UM10204 allows a push-pull SCL on a single-controller bus where no device stretches the clock. SDA stays open drain because the target drives ACKs and read data.
Source NXP UM10204 rev. 7 §3.1.1 SDA and SCL signals
Half-Truth
"A smaller pull-up is always better: faster edges."
Below Rp(min), a device cannot pull the line under VOL with its rated sink current. That current is 3 mA at 0.4 V for Sm/Fm. So a low is no longer a valid low.