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Interview Question · Code Writing

Sizing a Transistor with gm/ID

L1 JuniorL2 Mid-Levelmossizing

The interviewer asks

You need g_m = 200 µS from an NMOS at a chosen length. Describe, step by step, how you size it with the g_m/I_D method (g_m/I_D is transconductance per unit of drain current).

Reveal the Model Answer

Pick g_m/I_D for the trade you want: high for low current, low for speed. Then I_D is g_m divided by g_m/I_D. Read the current density I_D/W from a measured chart for that length, and get W as I_D over that density. Finally check g_m on a bench. The chart works in any inversion region, where the square law would not.

DC sweepgm/ID Against Current Density for Three LengthsNMOS with W = 2 µm at VDS = 0.9 V; the x axis is the base-10 logarithm of ID/W in A/µm, so −10.5 is 32 pA/µm, −9 is 1 nA/µm and −4 is 100 µA/µm.
  • L = 0.15 µm
  • L = 0.5 µm
  • L = 1 µm
051015202530gm/ID in 1/V-10-9-8-7-6-5-4log10 of I_D/W (A per µm)weak inversion above 20strong inversion below 100102030gm/ID in 1/V-10-8-6-4log10 of I_D/W (A per µm)weak inversion above 20strong inversion below 10
  1. log10 of I_D/W (A per µm) -10.5L = 0.15 µm = 25.18 · L = 0.5 µm = 26.45 · L = 1 µm = 28.31

    At 32 pA/µm every length is deep in weak inversion, flat at its limit 1/(n·UT): 25.2, 26.4 and 28.3 per volt.

  2. log10 of I_D/W (A per µm) -6.198L = 0.15 µm = 21.16 · L = 0.5 µm = 20 · L = 1 µm = 18.16

    The L = 0.5 µm curve crosses 20 at 0.634 µA/µm; above 20 we call a device weakly inverted.

  3. log10 of I_D/W (A per µm) -6L = 0.15 µm = 20.3 · L = 0.5 µm = 18.78 · L = 1 µm = 16.5

    At 1 µA/µm the lengths spread to 20.3, 18.8 and 16.5, because a longer device leaves weak inversion at a lower density.

  4. log10 of I_D/W (A per µm) -5.557L = 0.15 µm = 17.83 · L = 0.5 µm = 15 · L = 1 µm = 12.07

    L = 0.5 µm reaches 15 at 2.77 µA/µm, in the middle of moderate inversion, where the sizing example below starts.

  5. log10 of I_D/W (A per µm) -5L = 0.15 µm = 13.61 · L = 0.5 µm = 9.168 · L = 1 µm = 6.647

    At 10 µA/µm the values are 13.6, 9.17 and 6.65, and the long devices are now in strong inversion, below 10.

  6. log10 of I_D/W (A per µm) -4L = 0.15 µm = 4.114 · L = 0.5 µm = 2.295 · L = 1 µm = 1.427

    At 100 µA/µm gm/ID has fallen to 4.11, 2.29 and 1.43, so pushing more current through the same width buys little extra gm.

Read the plot as a table
log10 of I_D/W (A per µm)L = 0.15 µmL = 0.5 µmL = 1 µm
-10.525.1826.4528.31
-1025.1626.3528.15
-925.0425.8927.4
-824.6524.725.54
-723.4722.6722.44
-6.19821.162018.16
-620.318.7816.5
-5.55717.831512.07
-513.619.1686.647
-44.1142.2951.427

The measured chart this method reads: gm/ID against current density, one curve per length.

The Bench That Checks a Sized DeviceIB sets the drain current, and an amplifier compares the drain with 0.9 V and drives the gate, so VDS stays at 0.9 V whatever the device needs.
The bench that checks a sized device−++VDD1.8 VIB6.667 µAM3W/L = 2.4/0.5E1VREF0.9 Vd30.900 Vg30.715 V
  1. The current is set

    IB pushes 6.667 µA into the drain, and M3 must carry all of it.

    6.667 µA

  2. The amplifier finds the gate voltage

    If the drain rises above 0.9 V, the amplifier raises the gate, M3 conducts more and pulls the drain back down, until the loop settles with VGS = 0.715 V.

  3. Read gm

    Sweep IB a little and watch the gate: gm = ΔID/ΔVGS, and the lab measures 100.3 µS.

Read the circuit as text
  • IB current source (6.667 µA): + → VDD, − → d3
  • M3 NMOS transistor (W/L = 2.4/0.5): gate → g3, drain → d3, source → 0
  • E1 op-amp: −in → n1, +in → d3, out → g3
  • VREF voltage source (0.9 V): + → n1, − → 0
  • d3 = 0.900 V
  • g3 = 0.715 V

The last step: a bench that holds the sized device at its bias and measures gm.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Junior)

A good junior answer walks through the four steps in order. It explains what a high g_m/I_D costs and what a low one costs.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItCompareScale It

  1. Sizing a Transistor with gm/ID
  2. WhyWhy One Chart per Length Is EnoughL2 Mid-Level

    Why does one measured g_m/I_D chart per channel length size a device of any width?

    Reveal the Model Answer

    At a fixed length, g_m/I_D depends on how hard the channel is driven. The current density I_D/W captures that, not the width itself. Doubling W at the same density doubles I_D and g_m and leaves g_m/I_D unchanged. So one curve of g_m/I_D against density per length covers every width.

    Self-Check

    Tick each key point you covered in your answer.

  3. Prove ItSolve E5.3.1: A Bench for the Five-Transistor OTASimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem E5.3.1

  4. What IfChanging Length After Sizing from the ChartL2 Mid-Level

    What if you change the channel length after sizing from the chart? Can you keep the same chart?

    Reveal the Model Answer

    No. The chart holds for one length, because g_m/I_D at a given density changes with L. Take the chart for the new length and read a new density for the same g_m/I_D. A longer device gives more r_o and gain, but it adds capacitance and is slower.

    Self-Check

    Tick each key point you covered in your answer.

    Misconception

    "Keep W/L the same and the operating point does not change."

    That holds only under the square law. Short-channel effects change g_m/I_D at a fixed W/L, so read the chart for the new length.

    Source Lesson E2.5 key points

  5. CompareHigh vs Low gm/IDL1 JuniorL2 Mid-Level

    Compare biasing a transistor at high g_m/I_D with biasing it at low g_m/I_D.

    Reveal the Model Answer

    High g_m/I_D, near weak inversion, gives the most transconductance per microamp. But the device is wide and slow, and its threshold mismatch becomes a larger current error. Low g_m/I_D, strong inversion, costs current but gives small, fast devices and better current matching. Input pairs often sit high for noise and offset; mirrors and fast stages sit lower.

    Self-Check

    Tick each key point you covered in your answer.

  6. Scale ItDesigning an OTA to a SpecificationL2 Mid-LevelL3 Senior

    You get a brief for an OTA: load, unity-gain frequency, current budget, gain and input range. In what order do you size it?

    Reveal the Model Answer

    Start with f_u and C_L, which give g_m. The current budget then gives g_m/I_D (transconductance per unit current), and a measured chart gives W. The gain sets the length, and the input range checks the tail and the load. Keep margin on f_u, because the output node carries more than C_L. Check every line at every input level the brief names.

    From Brief to Sized OTAArrows show which number feeds the next decision.
    From brief to sized OTAArrows show which number feeds the next decision. component fu and CL 10 MHz into 2 pF component gm of M1 and M2 ≥ 125.7 µS; aim 157µS component Current budget 2 µA bias + 16 µA tail component gm/ID ≥ 19.6 /V; pick 22 component Width from chart 0.181 µA/µm: W = 40µm component Length for gain L = 1 µm for M1-M4 component Input range tail 8 × 8/2, load 4/1 component Simulate andcompare every line at 0.7, 0.9,1.1 V 2π·fu·CLI_D ≈ 8 µA
    1. Speed sets gm

      Into a capacitive load, fu = gm1/(2πCL), so gm1 ≥ 2π × 10 MHz × 2 pF = 125.7 µS. The output node carries more than CL, and the low end of the input range costs current, so aim 25 % higher: 157 µS.

    2. Current sets gm/ID

      Keep 2 µA for the bias diode and copy it eight times for a 16 µA tail: about 8 µA per input device. Then gm/ID ≥ 157/8 = 19.6 V−1. Pick 22, in moderate inversion.

    3. The chart sets W; gain sets L

      The chart below gives 0.181 µA/µm at gm/ID = 22, so W = 8 µA / 0.181 µA/µm = 44 µm: take 40. Gain is gm/(gds2 + gds4); at a fixed current only L moves the gds terms, and L = 1 µm clears 40 dB in E5.3's OTA.

    4. Range, then simulate

      The lower edge is VGS1 + VDsat5: a wide pair keeps VGS1 low and a wide tail (8 × 8/2) keeps VDsat5 low. The upper edge is VDD − VSG3 + Vth1: a 4/1 load keeps VSG3 small. Then run every line of the brief.

    Read the diagram as text
    • fu and CL: 10 MHz into 2 pF
    • gm of M1 and M2: ≥ 125.7 µS; aim 157 µS
    • Current budget: 2 µA bias + 16 µA tail
    • gm/ID: ≥ 19.6 /V; pick 22
    • Width from chart: 0.181 µA/µm: W = 40 µm
    • Length for gain: L = 1 µm for M1-M4
    • Input range: tail 8 × 8/2, load 4/1
    • Simulate and compare: every line at 0.7, 0.9, 1.1 V
    • fu and CL → gm of M1 and M2: 2π·fu·CL
    • gm of M1 and M2 → gm/ID
    • Current budget → gm/ID: I_D ≈ 8 µA
    • gm/ID → Width from chart
    • Width from chart → Length for gain
    • Length for gain → Input range
    • Input range → Simulate and compare

    Hand numbers come from formulas; the chart and the check come from runs.

    Self-Check

    Tick each key point you covered in your answer.

  7. Prove ItSolve E5.3.1: A Bench for the Five-Transistor OTASimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem E5.3.1

  8. Prove ItSolve E5.3.1: A Bench for the Five-Transistor OTASimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem E5.3.1

What People Get Wrong

Common wrong answers and why they fail.

Misconception

"g_m/I_D = 2/V_ov, so a small overdrive gives unlimited efficiency."

That is the square law. The device saturates at about 1/(n·U_T), 25 to 28 V⁻¹ for the sky130 1.8 V NMOS, once it enters weak inversion.

Source ASIC Point lesson E2.5 (measured; Jespers and Murmann, as cited)

Half-Truth

"Always bias at the highest g_m/I_D to save power."

High g_m/I_D needs wide devices with large capacitance, so the transistor gets slow. The choice is a trade between current, area and speed.

Learn It, Then Prove It