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Interview Question · Code Reading

The Five-Transistor OTA

L1 JuniorL2 Mid-Levelotaamplifier
  • Likely at NVIDIA

The interviewer asks

Read this five-transistor OTA netlist. What sets its DC gain and its unity-gain frequency, and which input is the + input?

spice
VDD vdd 0 1.8
IB vdd nb 20u
XMB nb nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XM5 tail nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XM1 x inp tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
XM2 out inn tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
XM3 x x vdd vdd sky130_fd_pr__pfet_01v8 W=8 L=1
XM4 out x vdd vdd sky130_fd_pr__pfet_01v8 W=8 L=1
CL out 0 1p
VIP inp 0 DC 0.9 AC 1
LF out inn 1T
Reveal the Model Answer

The PMOS mirror copies M1's current change to the output, so the full g_m·v_d reaches one node. DC gain is g_m(r_o2 ∥ r_o4), measured 42.71 dB. The unity-gain frequency is g_m/(2πC_L) and does not depend on r_o: 25.53 MHz here. The gate on the diode side, M1, is the + input. Check that sign open loop, because a buffer with swapped inputs still converges.

OTA-A, the Five-Transistor OTAM1 to M5 plus the bias diode MB. The gate of M1 is the + input, the gate of M2 the − input.
OTA-A, the five-transistor OTAVDD1.8 VM38/1M48/1M110/1M210/1IB20 µAMB8/1M58/1CL​1 pFout+−x0.618 Vout0.898 Vtail0.204 V
  1. Balance

    Both inputs at 0.9 V. M1 and M2 each carry about 9.3 µA. M3 takes M1's current, M4 copies it, and M2 takes the copy away: no current is left for CL.

    I · I

  2. Raise the + input

    M1 pulls Δi more. M3 carries it, so M4 pushes Δi more into the output. M2 pulls Δi less, because the tail current is fixed. Both changes push the output up: 2Δi flows into CL.

    I + Δi · I + Δi · 2Δi

  3. Raise the − input

    Now M2 pulls more and M1 less, so M4 pushes less: the output falls. The gate on the diode side is +, the gate on the output side is −.

Read the circuit as text
  • M3 PMOS transistor (8/1): gate → x, source → VDD, drain → x
  • M4 PMOS transistor (8/1): gate → x, source → VDD, drain → out
  • M1 NMOS transistor (10/1): gate → n1, drain → x, source → tail
  • M2 NMOS transistor (10/1): gate → n2, drain → out, source → tail
  • IB current source (20 µA): + → VDD, − → n3
  • MB NMOS transistor (8/1): gate → n3, drain → n3, source → 0
  • M5 NMOS transistor (8/1): gate → n3, drain → tail, source → 0
  • C_L capacitor (1 pF): pin 1 → out, pin 2 → 0
  • out port: terminal → out
  • + port: terminal → n1
  • − port: terminal → n2
  • x = 0.618 V
  • out = 0.898 V
  • tail = 0.204 V

Operating point of the lab at 0.9 V. NMOS bodies at ground, PMOS bodies at VDD. W/L in µm.

AC analysisOTA-A Open Loop into 1 pFGain and phase from the + input to the output.
  • gain
  • phase
-60 dB-40 dB-20 dB020 dB40 dB60 dBGain-180°-150°-120°-90°-60°-30°0Phase1 Hz100 Hz10 kHz1 MHz100 MHzFrequencyf_-3dBf_u-60 dB-40 dB-20 dB020 dB40 dB60 dBGain-180°-135°-90°-45°0Phase1 Hz1 kHz1 MHz1 GHzFrequencyf_-3dBf_u
  1. Frequency 10 Hzgain = 42.71 dB · phase = -0.003049°

    The DC gain A0 is 42.71 dB, 136.6 V/V, with 0° of phase: the output follows the + input.

  2. Frequency 187.5 kHzgain = 39.71 dB · phase = -44.97°

    The output pole: the gain is 3 dB down at 187.5 kHz and the phase has reached −45°.

  3. Frequency 25.53 MHzgain = -0.002124 dB · phase = -95.04°

    The gain crosses 0 dB at fu = 25.53 MHz, with a phase of −95.0°.

Read the plot as a table
Frequencygainphase
1 Hz42.71 dB-0.0002973°
10 Hz42.71 dB-0.003049°
100 Hz42.71 dB-0.0305°
1 kHz42.71 dB-0.305°
10 kHz42.7 dB-3.047°
100 kHz41.63 dB-28.03°
187.5 kHz39.71 dB-44.97°
1 MHz28.04 dB-79.57°
10 MHz8.185 dB-91.07°
25.53 MHz-0.002124 dB-95.04°
100 MHz-12.57 dB-109.5°
1 GHz-38.63 dB-145.5°

OTA-A open loop into 1 pF: 42.71 dB of DC gain and fu = 25.53 MHz, with -95° at fu.

The OTA-A bench from lesson E5.3: open loop on the 1 TH and 1 F bench, 1 pF load.

SPICEngspice 42 · simulator service
Edit the netlist, then run it

        
Expected: a0 = 4.271332e+01 f3db = 1.875369e+05 fu = 2.553041e+07 ph_fu = -9.503574e+01

        
        
      

          
Self-Check
Tick each key point you covered in your answer.


What Interviewers Listen For (Junior)
A good junior answer writes A_0 = g_m(r_o2 ∥ r_o4) and f_u = g_m/(2πC_L). It points to the gate that is the + input.


        

      

    

    
  

    

    

    
Cross-Questions

    
Where the interviewer goes next. Open a node to practise that follow-up.

    
WhyWhat IfProve ItCompareScale It

    
    
      
  1. The Five-Transistor OTA
    2. 
      
  2. 
    
    WhyThe Mirror Pole of a 5T OTAL2 Mid-Level
      
    
      
    Why is the phase at the unity-gain frequency of the 5T OTA a little worse than -90 degrees?
    
      
    
    
    
    
      
      
    Reveal the Model Answer
        
    The output pole gives -90 degrees. The mirror's diode node adds a second pole, set by its 1/g_m and the gate capacitance of both PMOS devices. That pole sits far above f_u, so it adds only a few degrees there. The lesson measured -95 degrees at f_u.
    
          
    Self-Check
    Tick each key point you covered in your answer.
    


        
    
      
    
    
    
    
  
    
      
    
    
    3. 

  3. 
    
    What IfWidening the Mirror DevicesL2 Mid-LevelL3 Senior
      
    
      
    What if you make the PMOS mirror devices much wider, for example to cut their flicker noise? What happens to that pole?
    
      
    
    
    
    
      
      
    Reveal the Model Answer
        
    The pole sits near g_m3 over the gate capacitance of both PMOS devices. At the same current, a wider device adds capacitance faster than it adds g_m. So the pole moves down toward f_u. It then costs more phase at f_u, and the phase margin drops.
    
          
    Self-Check
    Tick each key point you covered in your answer.
    


        
    
      
    
    
    
    
  
    
      
    
    
    Half-Truth
    
    
    "The mirror pole is far away, so the mirror size is free."
    
    
    Its frequency falls as the devices grow. Make them wide enough and the pole comes close to f_u.
    
    
    Source Lesson E5.3 key points
    
  
    
    
    4. 

  4. 
    
    CompareOne Stage vs Two StagesL1 JuniorL2 Mid-Level
      
    
      
    Compare a five-transistor OTA with a two-stage op-amp.
    
      
    
    
    
    
      
      
    Reveal the Model Answer
        
    The OTA has one high-impedance node, so it is stable by itself. But its gain is one intrinsic gain, 42.71 dB in the lesson. A two-stage op-amp adds a common-source stage, multiplying two gains: 80.84 dB. The second stage gives a second low-frequency pole, so it needs compensation. It also inverts, which moves the + input to the other gate.
    
          
    Self-Check
    Tick each key point you covered in your answer.
    


        
    
      
    
    
    
    
  
    
      
    
    
    5. 

  5. 
    
    Scale ItDesigning an OTA to a SpecificationL2 Mid-LevelL3 Senior
      
    
      
    You get a brief for an OTA: load, unity-gain frequency, current budget, gain and input range. In what order do you size it?
    
      
    
    
    
    
      
      
    Reveal the Model Answer
        
    Start with f_u and C_L, which give g_m. The current budget then gives g_m/I_D (transconductance per unit current), and a measured chart gives W. The gain sets the length, and the input range checks the tail and the load. Keep margin on f_u, because the output node carries more than C_L. Check every line at every input level the brief names.
    
    
    From Brief to Sized OTAArrows show which number feeds the next decision.
    

    
    
      From brief to sized OTAArrows show which number feeds the next decision.
    
    component
    fu and CL
    10 MHz into 2 pF
    
  
    
    component
    gm of M1 and M2
    ≥ 125.7 µS; aim 157µS
    
  
    
    component
    Current budget
    2 µA bias + 16 µA tail
    
  
    
    component
    gm/ID
    ≥ 19.6 /V; pick 22
    
  
    
    component
    Width from chart
    0.181 µA/µm: W = 40µm
    
  
    
    component
    Length for gain
    L = 1 µm for M1-M4
    
  
    
    component
    Input range
    tail 8 × 8/2, load 4/1
    
  
    
    component
    Simulate andcompare
    every line at 0.7, 0.9,1.1 V
    
  2π·fu·CLI_D ≈ 8 µA
    
    1. Speed sets gm
      Into a capacitive load, fu = gm1/(2πCL), so gm1 ≥ 2π × 10 MHz × 2 pF = 125.7 µS. The output node carries more than CL, and the low end of the input range costs current, so aim 25 % higher: 157 µS.
    2. Current sets gm/ID
      Keep 2 µA for the bias diode and copy it eight times for a 16 µA tail: about 8 µA per input device. Then gm/ID ≥ 157/8 = 19.6 V−1. Pick 22, in moderate inversion.
    3. The chart sets W; gain sets L
      The chart below gives 0.181 µA/µm at gm/ID = 22, so W = 8 µA / 0.181 µA/µm = 44 µm: take 40. Gain is gm/(gds2 + gds4); at a fixed current only L moves the gds terms, and L = 1 µm clears 40 dB in E5.3's OTA.
    4. Range, then simulate
      The lower edge is VGS1 + VDsat5: a wide pair keeps VGS1 low and a wide tail (8 × 8/2) keeps VDsat5 low. The upper edge is VDD − VSG3 + Vth1: a 4/1 load keeps VSG3 small. Then run every line of the brief.
    
  
    
    
    Read the diagram as text
    • fu and CL: 10 MHz into 2 pF
    • gm of M1 and M2: ≥ 125.7 µS; aim 157 µS
    • Current budget: 2 µA bias + 16 µA tail
    • gm/ID: ≥ 19.6 /V; pick 22
    • Width from chart: 0.181 µA/µm: W = 40 µm
    • Length for gain: L = 1 µm for M1-M4
    • Input range: tail 8 × 8/2, load 4/1
    • Simulate and compare: every line at 0.7, 0.9, 1.1 V
    • fu and CL → gm of M1 and M2: 2π·fu·CL
    • gm of M1 and M2 → gm/ID
    • Current budget → gm/ID: I_D ≈ 8 µA
    • gm/ID → Width from chart
    • Width from chart → Length for gain
    • Length for gain → Input range
    • Input range → Simulate and compare
    
    
    Hand numbers come from formulas; the chart and the check come from runs.
    
  
    
          
    Self-Check
    Tick each key point you covered in your answer.
    


        
    
      
    
    
    
    
  
    
      
    
    
    6. 

  6. 
    
    Prove ItSolve E5.3.1: A Bench for the Five-Transistor OTASimulator-graded
      
    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
    Open Problem E5.3.1
    
    
    7. 
    

  

    
What People Get Wrong
Common wrong answers and why they fail.

    
Misconception

    
"More output resistance gives a faster OTA."

    
Higher r_o raises the DC gain and lowers the output pole by the same factor. The unity-gain frequency g_m/(2πC_L) does not change.

    
Source ASIC Point lesson E5.3 (measured)

  

    
Tool as Truth

    
"If the buffer settles, the inputs are wired right."

    
A buffer with swapped inputs can still converge to a DC point in simulation. Check the sign open loop with a small step or the low-frequency phase.

    
Source ASIC Point lesson E5.3

  

    
Learn It, Then Prove It