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Interview Question · Debug
A Loop-Gain Bench That Lost Its Bias
- Likely at NVIDIA
The Question
The interviewer asks
To measure loop gain, a colleague cut the feedback wire and drove the opened input with an AC source. The result is below. What went wrong, and how should the loop be measured?
OPA-B, feedback cut and the input driven directly (lesson E6.5, measured)
operating point: output = 0.145 V (expected about 0.9 V)You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Cutting the loop removed the DC feedback that held the bias. So the output fell to 0.145 V, and the op-amp left its working state. A loop-gain bench must keep the DC bias and every load at the break point. A large inductor and capacitor break the loop for AC only. Middlebrook's method keeps the loop closed and combines a voltage run and a current run.
- The closed loop
The output drives the divider, the tap drives M1's gate, and OPA-B inverts it. Each link loads the one before it.
- LC break at the output
1 TH between the output and the divider, 1 F feeding the divider from the source. The source drives the divider directly, so the output no longer carries the divider's current.
- LC break at the gate
1 TH between the tap and the gate, 1 F feeding the gate. The divider still loads the output, but the tap no longer drives the gate's capacitance.
- Injection
A 0 V source in series between the output and the divider, and a current source into the output. Nothing is removed: each link keeps its load.
Read the diagram as text
- OPA-B: gain from the − input
- Output: drives C_L and the divider
- RF and RG: load the output
- Divider tap: RF and RG in parallel behind it
- M1 gate: a small capacitance
- OPA-B → Output: drives
- Output → RF and RG: current
- RF and RG → Divider tap: divides
- Divider tap → M1 gate: voltage
- M1 gate → OPA-B: returns
The LC break opens the loop for AC only: 1 TH carries the DC bias and blocks any signal; 1 F passes the signal and blocks DC.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer sees that the operating point is wrong. It keeps the DC loop closed with an inductor and capacitor break.
What Interviewers Listen For (Senior)
A good senior answer knows where the simple break is exact, and uses Middlebrook injection elsewhere. It checks a new bench on a loop with a known answer, and against a step.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItCompareScale It
- A Loop-Gain Bench That Lost Its Bias
-
WhyWhere the Simple Loop Break Is ExactL2 Mid-Level
Why is the inductor-and-capacitor loop break exact at an op-amp's output driving a gate, but not elsewhere?
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Reveal the Model Answer
Breaking the loop removes the load that one side of the break saw. At a stiff output driving a gate, that load was tiny, so nothing changes. Where the source impedance is high or the load is heavy, removing the load changes the gain and the poles. Then the measured margin is wrong.
AC analysisLoop Gain with 2 kΩ Resistors: Injection Against the LC Break at the OutputGain above, phase below. Each point marks fu. Whole plot- gain, injection
- gain, LC at output
- phase, injection
- phase, LC at output
- Frequency 10 Hzgain, injection = 38.88 dB · gain, LC at output = 74.82 dB · phase, injection = -0.006904° · phase, LC at output = -0.2494°
At 10 Hz injection reads 38.88 dB. The LC break at the output reads 74.82 dB: 36 dB too high.
- Frequency 7.271 MHzgain, injection = -0.003608 dB · gain, LC at output = 4.598 dB · phase, injection = -95.3° · phase, LC at output = -101.8°
Injection: |T| = 1 at 7.271 MHz with 84.7° of margin. The LC break at the gate (not drawn) agrees: 84.8°.
- Frequency 11.89 MHzgain, injection = -4.34 dB · gain, LC at output = -0.0001486 dB · phase, injection = -99.26° · phase, LC at output = -108.6°
The LC break at the output crosses at 11.89 MHz with 71.4°.
More context
With the divider fed from an ideal source, the output carries only CL. A 2 kΩ + 2 kΩ divider is the load that cut OPA-B's second-stage gain, and the bench took it away.
Read the plot as a table
Frequency gain, injection gain, LC at output phase, injection phase, LC at output 10 Hz 38.88 dB 74.82 dB -0.006904° -0.2494° 100 Hz 38.88 dB 74.81 dB -0.06904° -2.493° 1 kHz 38.88 dB 74.07 dB -0.6903° -23.53° 10 kHz 38.81 dB 61.82 dB -6.871° -77.08° 100 kHz 34.99 dB 42.04 dB -50.36° -88.85° 1 MHz 17.24 dB 22.04 dB -86.07° -91.52° 7.271 MHz -0.003608 dB 4.598 dB -95.3° -101.8° 10 MHz -2.806 dB 1.652 dB -97.67° -105.9° 11.89 MHz -4.34 dB -0.0001486 dB -99.26° -108.6° 100 MHz -25.8 dB -25.19 dB -152.4° -162.9° 1 GHz -61.16 dB -61.82 dB -296.3° -302.5° With 2 kΩ resistors the divider loads the output heavily. Breaking the loop there reads 36 dB too much gain.
Self-Check
Tick each key point you covered in your answer.
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CompareMiddlebrook Injection vs Breaking the LoopL2 Mid-LevelL3 Senior
Compare Middlebrook's injection method with breaking the loop with an inductor and a capacitor.
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Reveal the Model Answer
The inductor-and-capacitor break is one simple run, but it is exact only at a stiff node. Middlebrook's method keeps the loop closed and every load in place. It injects a series voltage in one run and a shunt current in another, then combines the two results. It works at any point in the loop, at the cost of two runs and a formula.
AC analysisLoop Gain with 200 kΩ Resistors: Injection Against the LC Break at the GateGain above, phase below. Each point marks fu. Whole plot- gain, injection
- gain, LC at gate
- phase, injection
- phase, LC at gate
- Frequency 10 Hzgain, injection = 70.65 dB · gain, LC at gate = 70.65 dB · phase, injection = -0.1555° · phase, LC at gate = -0.1555°
At 10 Hz both read 70.65 dB. The divider barely loads the output any more.
- Frequency 11.43 MHzgain, injection = -0.00366 dB · gain, LC at gate = 0.3306 dB · phase, injection = -123.2° · phase, LC at gate = -107.6°
Injection: |T| = 1 at 11.43 MHz with 56.8° of margin. The LC break at the output (not drawn) agrees: 56.5°.
- Frequency 11.83 MHzgain, injection = -0.3581 dB · gain, LC at gate = -0.00123 dB · phase, injection = -124.3° · phase, LC at gate = -108.2°
The LC break at the gate: 11.83 MHz and 71.8°, the number on the sign-off sheet.
More context
The gate shows 38.7 fF to the divider at fu. Behind the tap sit 200 kΩ ∥ 200 kΩ = 100 kΩ: a pole near 1/(2π·100 kΩ·38.7 fF) = 41.1 MHz that the closed loop has and this bench removes. At 11.4 MHz it costs atan(11.4/41.1) = 15.5°.
Read the plot as a table
Frequency gain, injection gain, LC at gate phase, injection phase, LC at gate 10 Hz 70.65 dB 70.65 dB -0.1555° -0.1555° 100 Hz 70.65 dB 70.65 dB -1.554° -1.554° 1 kHz 70.34 dB 70.34 dB -15.18° -15.18° 10 kHz 61.43 dB 61.43 dB -69.8° -69.78° 100 kHz 41.97 dB 41.97 dB -88.19° -88.05° 1 MHz 21.97 dB 21.98 dB -92.81° -91.41° 10 MHz 1.339 dB 1.597 dB -119.3° -105.6° 11.43 MHz -0.00366 dB 0.3306 dB -123.2° -107.6° 11.83 MHz -0.3581 dB -0.00123 dB -124.3° -108.2° 100 MHz -33.57 dB -25.17 dB -227.9° -161.4° 1 GHz -88.38 dB -61.6 dB -372.3° -289.1° With 200 kΩ resistors the output break and injection agree. The break at the gate still reads a margin that is too high.
Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve E6.5.1: A Phase-Margin Bench for a Gain of TwoSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
Scale ItMiller Compensation and the Right-Half-Plane ZeroL2 Mid-LevelL3 Senior
You compensate a two-stage op-amp with C_c across the second stage, and the margin is still poor. What else is C_c doing, and how do you fix it?
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Reveal the Model Answer
C_c splits the poles: it lowers the first pole and pushes the output pole up toward g_m6/(2πC_L). But C_c also feeds the signal forward to the output. That makes a right-half-plane zero at g_m6/(2πC_c), which lags the phase like a pole. A series R_z moves the zero. With R_z = 1/g_m6 it disappears, and a larger R_z turns it into phase lead.
OPA-B and Its Compensation NetworkCc in series with Rz connects o1 to out, across the second stage M6. Whole circuit- Two high-resistance nodes
o1 is loaded by M2, M4 and M6's gate; out by M6, M7 and CL. Without Cc their poles are close together.
- The Miller path
Cc bridges M6, whose gain is 96.7, so o1 sees Cc(1 + A2): 1 pF acts like 97.7 pF.
- M6 becomes a diode
At high frequency Cc shorts M6's gate to its drain. The output sees about 1/gm6 = 2.54 kΩ, and its pole moves up.
- The forward path
Cc also carries current from o1 straight into out, against M6's current. Where they are equal: a zero.
jωCc·vo1
- R_z
A series resistor changes that current, and with it where the zero sits.
Read the circuit as text
- IB current source (20 µA): + →
VDD, − →n1 - MB NMOS transistor (8/1): gate →
n1, drain →n1, source →0 - M3 PMOS transistor (8/1): gate →
n2, source →VDD, drain →n2 - M4 PMOS transistor (8/1): gate →
n2, source →VDD, drain →o1 - M1 NMOS transistor (10/1): gate →
n3, drain →n2, source →n4 - M2 NMOS transistor (10/1): gate →
n5, drain →o1, source →n4 - M5 NMOS transistor (8/1): gate →
n1, drain →n4, source →0 - M6 PMOS transistor (32/1): gate →
o1, source →VDD, drain →out - M7 NMOS transistor (16/1): gate →
n1, drain →out, source →0 - R_z resistor (0 to 10 kΩ): pin 1 →
o1, pin 2 →n6 - C_c capacitor (1 pF): pin 1 →
n6, pin 2 →out - C_L capacitor (2 pF): pin 1 →
out, pin 2 →0 - − inn port: terminal →
n3 - + inp port: terminal →
n5 - out port: terminal →
out
OPA-B as E5.5 defines it; W/L in µm. Bodies: NMOS to ground, PMOS to VDD.
AC analysisPole Splitting: OPA-B with C_c = 0 and 1 pFGain above, phase below. Rz = 0 and CL = 2 pF in both. Whole plot- gain, Cc 0
- gain, Cc 1 pF
- phase, Cc 0
- phase, Cc 1 pF
- Frequency 2.292 kHzgain, Cc 0 = 80.84 dB · gain, Cc 1 pF = 77.84 dB · phase, Cc 0 = -0.6459° · phase, Cc 1 pF = -44.94°
With 1 pF the gain is 3 dB down at 2.292 kHz. Without Cc the first pole sits at 225.3 kHz, 98 times higher.
- Frequency 20.79 MHzgain, Cc 0 = 20.4 dB · gain, Cc 1 pF = -0.003816 dB · phase, Cc 0 = -179.8° · phase, Cc 1 pF = -152.7°
With 1 pF the gain crosses 0 dB at 20.79 MHz, where the phase is −152.7°.
- Frequency 66.19 MHzgain, Cc 0 = -0.004216 dB · gain, Cc 1 pF = -13.97 dB · phase, Cc 0 = -194.9° · phase, Cc 1 pF = -219.8°
Without Cc the gain crosses 0 dB at 66.19 MHz, where the phase is −194.9°. That is past −180°, so a buffer made from it oscillates.
Read the plot as a table
Frequency gain, Cc 0 gain, Cc 1 pF phase, Cc 0 phase, Cc 1 pF 10 Hz 80.84 dB 80.84 dB -0.002817° -0.2495° 100 Hz 80.84 dB 80.83 dB -0.02818° -2.493° 1 kHz 80.84 dB 80.09 dB -0.2818° -23.53° 2.292 kHz 80.84 dB 77.84 dB -0.6459° -44.94° 10 kHz 80.83 dB 67.84 dB -2.816° -77.1° 100 kHz 80.07 dB 48.06 dB -26.75° -89.03° 1 MHz 66.67 dB 28.06 dB -106.3° -93.28° 10 MHz 33.03 dB 7.568 dB -171.1° -123° 20.79 MHz 20.4 dB -0.003816 dB -179.8° -152.7° 66.19 MHz -0.004216 dB -13.97 dB -194.9° -219.8° 100 MHz -7.551 dB -18.86 dB -202.8° -243° 1 GHz -46.93 dB -42.45 dB -270.3° -309.8° Pole splitting, measured. With Cc = 1 pF the first pole drops 98 times and the buffer no longer passes -180° at fu.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains pole splitting and names the right-half-plane zero. It fixes the zero with a nulling resistor.
What Interviewers Listen For (Senior)
A good senior answer designs at the heaviest load. It chooses between more second-stage current and a left-half-plane zero, and checks every load with a step.
Misconception
"A bigger C_c always buys more margin."
It lowers f_u but leaves the right-half-plane zero lagging the phase. On this op-amp, 1 pF with no R_z gives 27.3 degrees. With R_z = 5 kΩ the same C_c gives 60.1 degrees.
Run It
OPA-B open loop from lesson E6.4: C_c = 1 pF with R_z shorted (1 mΩ), 2 pF load.
SPICEngspice 42 · simulator serviceRun the netlist to draw its plots here.
Expected:pm = 2.731987e+01fz_hand = 6.260970e+07See the Fix
* E6.4 lab: OPA-B open loop on the inductor bench; C_c, R_z and C_L are parameters .lib sky130 tt .param cc=1p rz=5k cl=2p VDD vdd 0 1.8 IB vdd nb 20u XMB nb nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1 * stage one: M1 (diode side) takes the - input, M2 the + input XM5 tail nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1 XM1 x inn tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1 XM2 o1 inp tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1 XM3 x x vdd vdd sky130_fd_pr__pfet_01v8 W=8 L=1 XM4 o1 x vdd vdd sky130_fd_pr__pfet_01v8 W=8 L=1 * stage two XM6 out o1 vdd vdd sky130_fd_pr__pfet_01v8 W=32 L=1 XM7 out nb 0 0 sky130_fd_pr__nfet_01v8 W=16 L=1 * the compensation under test RZ o1 z {rz} CC z out {cc} CL out 0 {cl} * AC on the + input; 1 TH and 1 F close the loop for DC only, so v(out) is the loop gain T VIN inp 0 DC 0.9 AC 1 LF out inn 1T CF inn 0 1 .control op let gm1 = @m.xm1.msky130_fd_pr__nfet_01v8[gm] let gm6 = @m.xm6.msky130_fd_pr__pfet_01v8[gm] let ccv = @cc[capacitance] let rzv = @rz[resistance] let clv = @cl[capacitance] ac dec 50 1 10g let one = 1+0*vdb(out) let pmv = 180+180/pi*cph(v(out)) meas ac a0 FIND vdb(out) AT=10 meas ac fu WHEN vdb(out)=0 meas ac pm FIND pmv AT=fu * hand numbers: 1/gm6, p2 = gm6/(2 pi CL), and (for C_c above 0) f_u and the zero let rzn = 1/op1.gm6*one let p2h = op1.gm6/(2*pi*op1.clv)*one meas ac rz_null FIND rzn AT=10 meas ac p2_hand FIND p2h AT=10 if op1.ccv gt 0 let fuh = op1.gm1/(2*pi*op1.ccv)*one let fzh = 1/(2*pi*op1.ccv*(1/op1.gm6-op1.rzv))*one meas ac fu_hand FIND fuh AT=10 meas ac fz_hand FIND fzh AT=10 end .endc .endPrints:
pm = 6.008520e+01rz_null = 2.542018e+03fz_hand = -6.475026e+07Half-Truth
"Set R_z as large as possible to get the most phase lead."
Too large an R_z pushes f_u up into the higher poles and the margin falls again. Place the zero near the worst-case output pole, then measure.
Source ASIC Point lesson E6.4
- Two high-resistance nodes
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WhyWhy the Feed-Forward Zero HurtsL2 Mid-Level
Why does a right-half-plane zero hurt stability when an ordinary zero helps?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A left-half-plane zero adds phase lead as the gain rises. A right-half-plane zero raises the gain in the same way but adds phase lag instead. So it costs margin like a pole while it slows the gain's fall. In a Miller op-amp it comes from current that C_c passes forward from the first stage to the output.
AC analysisThe Second Stage Driven Alone, with and Without C_cvout/vo1: gain above, phase below. Rz = 0, CL = 2 pF. Whole plot- gain, Cc 1 pF
- gain, Cc 0
- phase, Cc 1 pF
- phase, Cc 0
- Frequency 1 kHzgain, Cc 1 pF = 39.71 dB · gain, Cc 0 = 39.71 dB · phase, Cc 1 pF = 179.7° · phase, Cc 0 = 179.8°
At 1 kHz the stage gives 39.71 dB and the phase is 179.7°: it inverts.
- Frequency 1 MHzgain, Cc 1 pF = 26.11 dB · gain, Cc 0 = 29.37 dB · phase, Cc 1 pF = 101.1° · phase, Cc 0 = 107.7°
Past the output pole the phase is 101.1° with Cc and 107.7° without. One pole has taken close to 90°.
- Frequency 59.54 MHzgain, Cc 1 pF = -6.147 dB · gain, Cc 0 = -5.69 dB · phase, Cc 1 pF = 45° · phase, Cc 0 = 87.24°
With 1 pF the phase reaches 45° at 59.54 MHz (hand: 62.6 MHz). Without Cc it is still 87.2°.
- Frequency 1 GHzgain, Cc 1 pF = -9.083 dB · gain, Cc 0 = -27.54 dB · phase, Cc 1 pF = 3.419° · phase, Cc 0 = 47.49°
With 1 pF the gain has flattened at −9.08 dB and the phase is 3.4°: out follows o1 through Cc. Without Cc: −27.54 dB and falling.
Read the plot as a table
Frequency gain, Cc 1 pF gain, Cc 0 phase, Cc 1 pF phase, Cc 0 1 kHz 39.71 dB 39.71 dB 179.7° 179.8° 10 kHz 39.7 dB 39.7 dB 177.3° 178.2° 100 kHz 38.85 dB 39.3 dB 154.8° 162.6° 1 MHz 26.11 dB 29.37 dB 101.1° 107.7° 10 MHz 6.421 dB 9.787 dB 81.62° 91.31° 59.54 MHz -6.147 dB -5.69 dB 45° 87.24° 100 MHz -7.82 dB -10.17 dB 30.74° 85.04° 1 GHz -9.083 dB -27.54 dB 3.419° 47.49° The second stage driven alone. With Cc the gain flattens at high frequency while the phase still lags: the zero in the right half-plane.
Self-Check
Tick each key point you covered in your answer.
-
WhyWhere the Right-Half-Plane Zero SitsL2 Mid-LevelL3 Senior
Why does the zero sit at g_m6/(2πC_c), and why does a bigger C_c not fix it?
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Reveal the Model Answer
At the zero, the current that C_c feeds forward equals the current the second stage sinks, so they cancel at the output. The forward current grows with frequency as s·C_c, and the stage current is set by g_m6. They meet at g_m6/(2πC_c). A bigger C_c lowers this zero, and it lowers f_u by the same factor.
Self-Check
Tick each key point you covered in your answer.
Misconception
"Make C_c bigger to push the zero away."
A bigger C_c lowers the zero frequency. It also lowers f_u = g_m1/(2πC_c), so the ratio between them stays g_m6/g_m1.
Source Lesson E6.4 key points
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What IfNulling the Zero with R_z = 1/g_m6L2 Mid-LevelL3 Senior
Asked if they set R_z to exactly 1/g_m6
What if you set R_z exactly to 1/g_m6, about 2.54 kΩ here, as in the parameter line below?
spice .param cc=1p rz=2542 cl=2p RZ o1 z {rz} CC z out {cc} CL out 0 {cl}2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
The zero moves out to a very high frequency, so it no longer lags the phase. On this op-amp the margin rises from 27.3 to 45.1 degrees. That is better but still short of 60, because the output pole is still close to f_u. A slightly larger R_z, here 5 kΩ, puts a helpful zero near that pole.
AC analysisLoop Phase with C_c = 1 pF and Four Values of R_zEach point marks fu. CL = 2 pF. Whole plot- Rz 0
- Rz 2.54 kΩ
- Rz 5 kΩ
- Rz 10 kΩ
- Frequency 20.33 MHzRz 0 = -151.6° · Rz 2.54 kΩ = -134.9° · Rz 5 kΩ = -118.8° · Rz 10 kΩ = -95.21°
With Rz = 2.54 kΩ the zero is gone: 45.1° of margin at 20.33 MHz.
- Frequency 21.43 MHzRz 0 = -154.2° · Rz 2.54 kΩ = -136.8° · Rz 5 kΩ = -119.9° · Rz 10 kΩ = -96.05°
With 5 kΩ a left-half-plane zero near 65 MHz lifts the margin to 60.1°.
- Frequency 31.89 MHzRz 0 = -176.1° · Rz 2.54 kΩ = -152.2° · Rz 5 kΩ = -129.2° · Rz 10 kΩ = -105.5°
With 10 kΩ the zero near 21 MHz lifts the gain too, so fu moves up to 31.89 MHz, with 74.5° of margin.
Read the plot as a table
Frequency Rz 0 Rz 2.54 kΩ Rz 5 kΩ Rz 10 kΩ 100 kHz -89.03° -88.94° -88.85° -88.67° 1 MHz -93.28° -92.38° -91.5° -89.72° 10 MHz -123° -114.2° -105.7° -89.89° 20.33 MHz -151.6° -134.9° -118.8° -95.21° 21.43 MHz -154.2° -136.8° -119.9° -96.05° 31.89 MHz -176.1° -152.2° -129.2° -105.5° 100 MHz -243° -201.6° -161.6° -160.1° 1 GHz -309.8° -293.5° -278.3° -273.1° Measured on ngspice 42; the table lists all nine copies of the run.
SPICEngspice 42 · simulator serviceRun the netlist to draw its plots here.
Expected:pm = 4.512441e+01rz_null = 2.542018e+03Self-Check
Tick each key point you covered in your answer.
-
CompareMore Current vs a Placed ZeroL3 Senior
Compare two ways to meet a 10 MHz target at a 5 pF load: more second-stage current, or a zero placed with R_z.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
With the zero cancelled, f_u must stay below the output pole divided by 2.2. In the lesson that capped the op-amp at 5.77 MHz, and 10 MHz needed 2.5 times the second-stage current. Placing a left-half-plane zero near the worst output pole met the brief at the original current, with 1.75 pF and 8 kΩ. The price is sensitivity to R_z and to the load.
The Compensation Method, with the Measured NumbersArrows show the order of the decisions. Illustrative sequence- Find the worst case
The output pole falls with CL, so 5 pF decides the design.
- The textbook route
With the zero cancelled, 60° at 5 pF allows only 5.77 MHz. Doubling the bandwidth needs about 2.5 times the second-stage current.
- Use the zero
A left-half-plane zero near p2 recovers the phase at the original current. Then verify every load, the step, and Rz 20 % off.
Read the diagram as text
- Brief: 60°, 10 MHz, 1 to 5 pF
- Worst load: 5 pF: p2 near 12.5 MHz
- Cancel the zero: Rz = 1/gm6: 5.77 MHz
- More current: 2.5x stage two: 254 uW
- Use the zero: Rz = 8 k, Cc = 1.75 pF
- Verify: every load, a step, Rz +-20 %
- Brief → Worst load: find
- Worst load → Cancel the zero: try
- Cancel the zero → More current: too slow
- Cancel the zero → Use the zero: or
- Use the zero → Verify: measure
- More current → Use the zero: compare
Every number is from the comparison run in the next figure.
Self-Check
Tick each key point you covered in your answer.
- Find the worst case
-
Prove ItSolve E6.6.1: Stable from 1 to 5 pF on Less CurrentSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Prove ItSolve E6.4.1: The Buffer That a Bigger C_c SlowedSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Half-Truth
"The 1 TH and 1 F break is exact anywhere in the loop."
It is exact only where a stiff node drives a much higher impedance up to f_u. On one gain-of-two amplifier it was 13 degrees off at the output with 2 kΩ, and 15 degrees off at a gate with 200 kΩ.
Source ASIC Point lesson E6.5 (measured)
Delivery
"Trust the margin from the bench; no need for a step."
A bench can be wrong in ways the AC plot does not show. Check it on a loop whose loop gain you know, and cross-check the margin against a step response.