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Interview Question · Project Defence

Defending the Reset Scheme of Your Block

L2 Mid-LevelL3 Seniorresetproject defence

The interviewer asks

Walk me through the reset scheme of a block you designed. Which flops did you reset, and why?

Reveal the Model Answer

Start with the goals: a known state after reset, a safe release, and no wasted area. Then give the scheme: asynchronous assert, a synchronizer per clock domain, and the release order. Reset every control flop: states, valid bits, counters and pointers. Datapath flops can skip reset when a reset valid bit guards them. Close with how you verified it, including reset in the middle of traffic.

Two Events Sent into a Sleeping DomainThe lab design. Every value is sampled 1 ns after an edge of the sender's clock clk, edges 2 to 24. t2 is the receiver's synchronized copy of the toggle; got counts the events it has received.
012345678910111213141516171819202122clkrst_a_nrst_b_ntog_at2gotB out of reset
  1. Cycle 1

    Edge 3: the sender's domain is out of reset, so ready_a is 1.

  2. Cycle 2

    Edge 4: event 1. The toggle goes to 1 while the receiver is still in reset.

  3. Cycle 10

    Edge 12: event 2. The toggle goes back to 0, still before the receiver wakes.

  4. Cycle 14

    Edge 16: the receiver is out of reset, and its flops read a toggle of 0, the same as their reset value. Events 1 and 2 left no trace.

  5. Cycle 22

    Edge 24: event 3, sent at edge 20, arrives. Three sent, one received.

Measured in lesson R6.5: two events sent while the other domain was still in reset left no trace. A reset scheme must state the release order.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Mid-Level)

A good mid-level answer names which flops are reset and why. It says how the valid bit protects data flops that have no reset.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyBreak ItCompareScale It

  1. Defending the Reset Scheme of Your Block
  2. WhyWhy Datapath Flops Can Skip ResetL2 Mid-Level

    Why is it safe to leave the data flops unreset?

    Reveal the Model Answer

    Nothing reads the data until the valid bit says it is good, and the valid bit is reset to 0. The first valid beat loads real data into the flops at the same edge. Flops without reset pins are smaller and need no reset wiring. The rule breaks if any logic uses the data without checking valid.

    Self-Check

    Tick each key point you covered in your answer.

    Half-Truth

    "Unreset flops make X-propagation checks fail, so they are a bug."

    X in guarded data is expected. A check should target control signals and data that is used while valid is 1.

    Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 8.1.5.1 Non-resettable RTL flip-flop models

  3. Break ItThe Reader That Breaks Unreset DataL2 Mid-Level

    Break it: what later change makes the unreset data flops a bug?

    Reveal the Model Answer

    Any logic that reads the data without checking valid. A debug counter or a parity check on the raw data are typical. After reset those flops hold unknown values, so the new logic sees X in simulation and random values in silicon. Guard every reader with valid.

    Self-Check

    Tick each key point you covered in your answer.

    Missed Corner

    "Simulation shows X there, so we would notice."

    Only if a check reads it. An if on X takes the else branch, and a two-state run shows a plain 0.

    Source IEEE 1800-2017 §12.4

  4. Break ItReset and No-Reset Flops in One BlockL2 Mid-LevelL3 Senior

    How can the reset scheme break in the code itself? What does synthesis build for out_data here?

    systemverilog
    module stage (input logic clk, rst_n, in_valid, input logic [7:0] in_data,
              output logic out_valid, output logic [7:0] out_data);
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) out_valid <= 1'b0;              // only valid is reset
    else begin
      out_valid <= in_valid;
      out_data  <= in_data;                     // no reset, but in the same block
    end
endmodule
    Reveal the Model Answer

    The data is not reset, but it sits in the else of the reset if. So out_data must hold its value while reset is asserted. Synthesis adds that hold as an enable. On this flow the 8 data flops became enabled flops with rst_n as the enable. Put unreset flops in their own always_ff, without the reset in the list.

    module stage (input logic clk, rst_n, in_valid, input logic [7:0] in_data,
              output logic out_valid, output logic [7:0] out_data);
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) out_valid <= 1'b0;              // only valid is reset
    else begin
      out_valid <= in_valid;
      out_data  <= in_data;                     // no reset, but in the same block
    end
endmodule

    Self-Check

    Tick each key point you covered in your answer.

    Misconception

    "Leaving a register out of the reset branch just means it has no reset."

    It also means "do not change during reset", which is extra logic: an enable or a mux on every bit.

    Source Cummings, Mills and Golson, Asynchronous & Synchronous Reset Design Techniques - Part Deux (SNUG Boston 2003) §3.1

  5. CompareA Reset vs an Initial ValueL1 JuniorL2 Mid-Level

    Compare a reset with an initial value such as logic [3:0] cnt = 0;. Can the initial value replace the reset?

    Reveal the Model Answer

    On many FPGAs, yes: the bitstream loads flops with their initial values at power-up. On an ASIC, no. Flops power up unknown, and the initial value exists only in simulation. An ASIC block needs a reset, and it then works the same on both targets.

    Self-Check

    Tick each key point you covered in your answer.

    Misconception

    "The initial value works in simulation, so it works in the chip."

    Simulation applies it at time zero. ASIC flops have no such load, so the gates start unknown.

    Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 3.4 Variable types, Best Practice Guidelines 3-5 and 3-6

  6. Scale ItReset Domain CrossingsL3 Senior

    Scale the scheme up. Your block has a soft reset for one part and none for the rest. What can go wrong?

    Reveal the Model Answer

    When the soft reset asserts, its flops change at once, at no fixed time relative to the clock. A flop that is not in reset may sample one of them at that moment. Even on one clock, that path now behaves like an asynchronous crossing. Fix it by holding the receiver too, or by gating the path while the soft reset is active.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Senior)

    A good senior answer spots the crossing that a partial reset creates, even on a single clock. It asks for RDC (reset domain crossing) analysis next to CDC.

    Misconception

    "One clock means no crossing, so no synchronizer is needed."

    An asynchronous reset changes a flop at any time. A receiver that keeps running can sample it mid-change and go metastable.

    Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 8.1.6 Multiple clocks and clock domain crossing (metastability when an input changes near the clock)

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Missed Corner

"The valid bit is in the datapath, so it does not need a reset either."

A valid bit is control. Unreset, it starts as X, and the block may act on garbage. The twin shows out_valid stuck at X after reset.

Run It

A pipeline stage with no reset on out_valid, then with the valid bit reset and the data left unreset.

RUNIcarus Verilog · in your browser
Edit the code, then run it

        
Expected: after reset: out_valid=x FAIL: the valid bit is control, not data; unreset it starts as X, not 0

        
        
      

      
See the Fix
module stage (input logic clk, rst_n, in_valid, input logic [7:0] in_data,
              output logic out_valid, output logic [7:0] out_data);
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) out_valid <= 1'b0;              // the control bit is reset
    else        out_valid <= in_valid;
  always_ff @(posedge clk)
    out_data <= in_data;                        // data: no reset, guarded by out_valid
endmodule
module tb;
  logic clk = 0, rst_n, in_valid = 0, out_valid; logic [7:0] in_data = 0, out_data;
  stage dut (.*);
  always #5 clk = ~clk;
  initial begin
    #1 rst_n = 1; #1 rst_n = 0;                  // power-on reset pulse
    #1 rst_n = 1;                                // released before the first edge
    #1 $display("after reset: out_valid=%b", out_valid);
    if (out_valid === 1'b0) $display("PASS: out_valid is 0 after reset; the data flops may stay X");
    $finish;
  end
endmodule

Prints: after reset: out_valid=0 PASS: out_valid is 0 after reset; the data flops may stay X

    

  

    
Wrong Altitude

    
"I reset every flop, to be safe."

    
From a senior, this skips the trade-off. Reset on wide datapath registers costs area and reset-tree routing and buys nothing when a valid bit guards them.

    
Source Sutherland, RTL Modeling with SystemVerilog (2017) ch. 8.1.5.1 Non-resettable RTL flip-flop models

  

    
Delivery

    
Lists signal names for five minutes with no structure.

    
The interviewer wants goals, the scheme, the choices and the proof. A list of names shows neither judgement nor ownership.

  

    
Learn It, Then Prove It