IR Drop and Electromigration

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WhyProve ItBreak ItCompareScale It

1. IR Drop and Electromigration
2. WhyWhy Rail Drop Grows with the Square of the SpacingL2 Mid-Level

   Why does the drop in the middle of a rail grow with the square of the strap spacing?

   Reveal the Model Answer

   Doubling the spacing doubles two things. It doubles the current the middle of the rail must carry, since twice as many cells feed through it. It also doubles the resistance that current flows through. With uniform load and both ends held at the supply, the peak drop is j·r·D²/8. Lesson L3.5 checks that model against a measured rail and finds it close.

   Read the circuit as text

   • r·Δx resistor: pin 1 → n1, pin 2 → strap A
   • r·Δx resistor: pin 1 → n2, pin 2 → n1
   • r·Δx resistor: pin 1 → strap B, pin 2 → n2
   • j·Δx current source: + → n1, − → 0
   • j·Δx current source: + → n2, − → 0

   Each Δx of rail is a resistor; each cell is a current sink. The drop grows toward the middle.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Doubling the spacing doubles two things. Key point 2 It doubles the current the middle of the rail must carry, since twice as many cells feed through it. Key point 3 It also doubles the resistance that current flows through. Key point 4 With uniform load and both ends held at the supply, the peak drop is j·r·D²/8. Key point 5 Lesson L3.5 checks that model against a measured rail and finds it close.

   • Lesson L3.5IR Drop and Electromigration
3. CompareStatic vs Dynamic IR DropL2 Mid-LevelL3 Senior

   Compare static and dynamic IR-drop analysis.

   Reveal the Model Answer

   Static analysis applies each cell's average current from power analysis and solves the grid once, which finds weak straps and long rails. Dynamic analysis follows current over time. So it sees many cells switching together after a clock edge, and the local droop that decaps must cover. A block can pass static analysis and still fail dynamic, so sign-off states which one ran and with what activity.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Static analysis applies each cell's average current from power analysis and solves the grid once, which finds weak straps and long rails. Key point 2 Dynamic analysis follows current over time. Key point 3 So it sees many cells switching together after a clock edge, and the local droop that decaps must cover. Key point 4 A block can pass static analysis and still fail dynamic, so sign-off states which one ran and with what activity.

   • Lesson L3.5IR Drop and Electromigration
   • Lesson L7.4Fill: Cells, Metal and Density
4. Break ItWhy a Flat Voltage Derate Is Not a ModelL2 Mid-LevelL3 Senior

   Someone adds the derate below to the SDC and calls IR drop covered. What does that line really do?

   create_clock -name clk -period 0.6 [get_ports clk]
   set_timing_derate -late 1.05 -cell_delay

   Reveal the Model Answer

   It makes every cell 5 % slower everywhere on the late paths, whatever the drop at that cell actually is. It is easy to run and says nothing about where the grid is weak or how this library's delay changes with voltage. On the lesson's path it moved the slack from 0.1462 to 0.1291 ns, a number with no physical basis.

   ff1 → ff2setup check, latest arrival3 cells

   • Clock latency
   • Cell delay
   • Setup time

   1. Arrival

      Clock-to-Q and two gates: the data arrives at 0.3423 ns. Every one of those delays assumes 1.8 V.

   2. Slack

      Required at 0.4885 ns, so the slack is 0.1462 ns.

   Read the path as a table

   Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 0.6000 ns, latency 0.0000 ns, library setup time −0.1115 ns.

   Arrival 0.3423 ns, required 0.4885 ns, slack 0.1462 ns (met).

   Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
   1	ff1/CLK → ff1/Q	dfxtp_1	fall	0.2716	0.2716	0.0250
   	ff1/Q → u1/A	wire q1	fall	0.0000	0.2716	0.0250
   2	u1/A → u1/Y	inv_1	rise	0.0377	0.3092	0.0299
   	u1/Y → u2/A	wire n1	rise	0.0000	0.3092	0.0299
   3	u2/A → u2/Y	nand2_1	fall	0.0331	0.3423	0.0233
   	u2/Y → ff2/D	wire n2	fall	0.0000	0.3423	0.0233

   The report

   Startpoint: ff1 (rising edge-triggered flip-flop clocked by clk)
   Endpoint: ff2 (rising edge-triggered flip-flop clocked by clk)
   Path Group: clk
   Path Type: max
   
   Fanout       Cap      Slew     Delay      Time   Description
   -------------------------------------------------------------------------------------
                       0.0000    0.0000    0.0000   clock clk (rise edge)
                                 0.0000    0.0000   clock network delay (ideal)
                       0.0000    0.0000    0.0000 ^ ff1/CLK (sky130_fd_sc_hd__dfxtp_1)
        1    0.0022    0.0250    0.2716    0.2716 v ff1/Q (sky130_fd_sc_hd__dfxtp_1)
                                                    q1 (net)
                       0.0250    0.0000    0.2716 v u1/A (sky130_fd_sc_hd__inv_1)
        1    0.0024    0.0299    0.0377    0.3092 ^ u1/Y (sky130_fd_sc_hd__inv_1)
                                                    n1 (net)
                       0.0299    0.0000    0.3092 ^ u2/A (sky130_fd_sc_hd__nand2_1)
        1    0.0017    0.0233    0.0331    0.3423 v u2/Y (sky130_fd_sc_hd__nand2_1)
                                                    n2 (net)
                       0.0233    0.0000    0.3423 v ff2/D (sky130_fd_sc_hd__dfxtp_1)
                                           0.3423   data arrival time
   
                       0.0000    0.6000    0.6000   clock clk (rise edge)
                                 0.0000    0.6000   clock network delay (ideal)
                                 0.0000    0.6000   clock reconvergence pessimism
                                           0.6000 ^ ff2/CLK (sky130_fd_sc_hd__dfxtp_1)
                                -0.1115    0.4885   library setup time
                                           0.4885   data required time
   -------------------------------------------------------------------------------------
                                           0.4885   data required time
                                          -0.3423   data arrival time
   -------------------------------------------------------------------------------------
                                           0.1462   slack (MET)

   The path before the flat derate: slack 0.1462 ns. The derate only moves this number; it adds no physics.

   create_clock -name clk -period 0.6 [get_ports clk]
   set_timing_derate -late 1.05 -cell_delay
   

   Prints: 0.1291 slack (MET)

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 It makes every cell 5 % slower everywhere on the late paths, whatever the drop at that cell actually is. Key point 2 It is easy to run and says nothing about where the grid is weak or how this library's delay changes with voltage. Key point 3 On the lesson's path it moved the slack from 0.1462 to 0.1291 ns, a number with no physical basis.

   • Lesson L3.5IR Drop and Electromigration
5. Scale ItA Denser Grid vs Routing ResourcesL2 Mid-LevelL3 Senior

   Compare halving and doubling the met4 strap pitch. What do you gain and lose?

   Reveal the Model Answer

   Halving the pitch cuts IR drop and costs routing tracks; doubling it frees tracks and raises the drop. Lesson L3.5 used a 3324-cell block. There the worst drop went from 0.00148 V to 0.00069 V with half the pitch, and to 0.00332 V with double. The met4 routing resources moved from 9268 to 7880 and 9924. Measure both sides before you choose.

   • Platform grid
   • met4 pitch doubled
   • met4 pitch halved

   Read the plot as a table

   Position across the core	Platform grid	met4 pitch doubled	met4 pitch halved
   50 µm	26 µV	73.92 µV	12.54 µV
   100 µm	68.53 µV	168.2 µV	24.18 µV
   150 µm	158.4 µV	517.4 µV	57.41 µV
   200 µm	697.3 µV	1.479 mV	414.2 µV
   250 µm	96.39 µV	656.5 µV	31 µV

   Measured with PDNSim (the OpenROAD IR-drop tool) on one placement. A wider met4 pitch gives a deeper drop.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Halving the pitch cuts IR drop and costs routing tracks; doubling it frees tracks and raises the drop. Key point 2 Lesson L3.5 used a 3324-cell block. Key point 3 There the worst drop went from 0.00148 V to 0.00069 V with half the pitch, and to 0.00332 V with double. Key point 4 The met4 routing resources moved from 9268 to 7880 and 9924. Key point 5 Measure both sides before you choose.

   • Lesson L3.5IR Drop and Electromigration
   • Lesson L3.4The Power Grid and Well Taps
   • Problem L3.5.1Spend Fewer Straps on the Grid
6. Prove ItSolve L3.5.1: Spend Fewer Straps on the GridSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L3.5.1

7. WhyWhy Rail Drop Grows Faster Than the PitchL2 Mid-LevelL3 Senior

   Why did doubling the pitch more than double the worst drop?

   Reveal the Model Answer

   Between two straps, a rail with uniform load drops most at the middle, by j·r·D²/8. So that part grows with the square of the spacing D. The measured worst drop went from 0.00148 V to 0.00332 V, about 2.2 times. The rail part is only one share of the total, so the growth is less than four times.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Between two straps, a rail with uniform load drops most at the middle, by j·r·D²/8. Key point 2 So that part grows with the square of the spacing D. Key point 3 The measured worst drop went from 0.00148 V to 0.00332 V, about 2.2 times. Key point 4 The rail part is only one share of the total, so the growth is less than four times.

   Misconception

   "IR drop scales in proportion to the strap pitch."

   The rail drop between straps grows with the square of the spacing. Doubling the pitch can more than double that part.

   Source Lesson L3.5 key points

   • Lesson L3.5IR Drop and Electromigration
   • Problem L3.5.1Spend Fewer Straps on the Grid