Interview Question · Concept
Pin Placement and Its Hidden Cost
- Likely at Samsung
The Question
The interviewer asks
Why does the position of a block's I/O pins change the wirelength of nets that never touch a pin?
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Reveal the Model Answer
The placer pulls cells toward the pins they connect to. So a poor pin plan drags whole cones of logic toward one edge. It also stretches the internal nets between them. In lesson L3.2, putting all 39 pins on the left edge raised placed wirelength from about 6041 to 7365 µm. The I/O nets were only part of it. Pin edges are also an agreement with the top level, so plan them early.
Read the diagram as text
- All 39 pins on the left edge
- Placer pulls connected cells left
- Internal nets stretch
- Placed wire 7365 µm
- Flow pin plan: Each pin near the cells that use it
- Placed wire 6041 µm
- All 39 pins on the left edge → Placer pulls connected cells left
- Placer pulls connected cells left → Internal nets stretch
- Internal nets stretch → Placed wire 7365 µm
- Flow pin plan → Placed wire 6041 µm
The I/O nets are only part of the cost. The cells that follow the pins drag their own nets too.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer says the placer pulls cells toward the pins they connect to. So the pin positions also shape the wirelength inside the block.
What Interviewers Listen For (Senior)
A good senior answer agrees the pin edges with the top level, starting from the data flow. It keeps each bus together. It measures the effect with a placement run before it freezes the plan.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItCompare
- Pin Placement and Its Hidden Cost
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WhyWhich Layer Each Pin Edge UsesL1 Junior
In a sky130 block, why do the left and right pins sit on met3, but the top and bottom pins on met2?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A pin is reached by a wire running into the edge. So it uses a layer whose preferred direction points into that edge. Layer met3 runs horizontally, which suits the left and right edges, and met2 runs vertically, which suits the top and bottom. A pin on the wrong layer forces a wire against its preferred direction, which blocks tracks.
Self-Check
Tick each key point you covered in your answer.
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CompareComparing Pin PlansL2 Mid-Level
Compare putting the inputs on the bottom and the outputs on the top with the flow's own pin plan.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
For the lesson's MAC, inputs on the bottom and outputs on the top gave about 6853 µm of placed wire. The flow's plan gave 6041 µm. The flow spreads each pin near the cells that use it. A data-flow plan is still often the right call when the top level needs it. The point is to measure the cost of the plan the parent wants rather than guess it.
Self-Check
Tick each key point you covered in your answer.
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Prove ItSolve L6.3.1: Give the Crossbar Pins RoomSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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What IfA Bus Moved to the Other Edge After PlacementL2 Mid-LevelL3 Senior
Asked if they say pins can be fixed later
After placement, the top level asks you to move a 32-bit bus to the opposite edge of your block. What do you check before agreeing?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Re-run placement with the new pin plan. Compare wirelength, congestion near the new edge and the timing of the paths through the bus. The cells that talk to the bus will migrate, so internal paths can move too, not only the I/O nets. Agree only with the measured cost in hand, and update the I/O budgets with the parent, because the boundary delays change.
Self-Check
Tick each key point you covered in your answer.
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What IfKeeping the Old I/O Budget After a Pin MoveL2 Mid-LevelL3 Senior
What if the bus moves but nobody updates the input and output delays?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Then the boundary paths are signed off against delays that no longer exist. The new edge changes the wire length on both sides of the pin. Re-derive the input and output delays with the parent, from the new floorplan. Until then, list the I/O paths as open.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"The block meets its I/O budget, so the top level will close."
Only if the budget matches the real wires outside. A moved pin changes them, so the old budget no longer describes the chip.
What People Get Wrong
Common wrong answers and why they fail.
Misconception
"Pin positions only affect the I/O nets."
Cells move toward their pins, so the internal nets stretch too. In the lesson the I/O-net share of the 1324 µm increase was 575 µm.
Source ASIC Point lesson L3.2 (measured build-only runs)
Wrong Altitude
"Let the tool place pins randomly and fix it later."
Pins are an interface contract with the top level, and the random option is obsolete in the pinned build. Moving them late ripples into the parent floorplan.