Interview Question · Design
A Late Timing and Functional ECO
- Likely at Broadcom
- Likely at NVIDIA
- Likely at Synopsys
The Question
The interviewer asks
After routing, you need both a timing fix on two paths and a small logic correction. How do you make the changes and prove nothing else broke?
You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
Write down the intended behaviour and the physical changes you will allow before touching the layout. Make the timing fix with local resizing or buffering. Make the logic fix with spare cells or minimal new ones. Then legalize, route incrementally and measure every changed cell and connection. Prove the logic fix by equivalence against the corrected RTL. Refresh timing at every corner, plus DRC, LVS and antenna, on the result.
Read the diagram as text
- Corrected RTL: Packet behavior
- Mapped circuit: Pinned cells and constraints
- Placed and routed block: Clock tree · repair · wires
- Reviewed handoff: Final views · reports · open work
- Corrected RTL → Mapped circuit: Synthesize and verify
- Mapped circuit → Placed and routed block: Implement and extract
- Placed and routed block → Reviewed handoff: Check and document
An ECO is a late edit. Every report the edit touches must be run again on the new data.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer keeps the timing ECO separate from the functional ECO, and limits the physical change. It re-runs equivalence and the timing of every corner.
What Interviewers Listen For (Staff)
A good staff answer plans spare cells and free floorplan space for ECOs in advance. It controls who may change what after the freeze. It puts the full sign-off rerun into the ECO budget.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItBreak ItCompare
- A Late Timing and Functional ECO
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WhyWhy an ECO Needs Equivalence CheckingL2 Mid-LevelL3 Senior
Why prove a functional ECO with equivalence checking against corrected RTL?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
The edited netlist no longer comes from synthesis, so nothing ties it to the RTL except the check. Equivalence against the corrected RTL shows the whole function now matches, not just the failing case. In lesson L7.5 the corrected netlist was proven against corrected RTL. The original netlist was not, and the lesson records it as unproven.
Self-Check
Tick each key point you covered in your answer.
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CompareSpare Cells vs New Cells for an ECOL2 Mid-LevelL3 Senior
Compare making a functional fix with pre-placed spare cells against adding new cells.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Spare cells are already placed. So a fix that only rewires them can be done in the metal layers, which limits the change. New cells give exactly the gates you need but must be placed, which can move neighbours and touch the base layers. Lesson L7.5's problem asks for a reconnection without new base cells for that reason.
Self-Check
Tick each key point you covered in your answer.
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What IfHold Repair Across Four CornersL2 Mid-LevelL3 Senior
Asked if they re-time only the corner that failed
Your hold repair passes at the fast corner but fails setup at the slow corner. How do you close both?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Repair against all required corners at once. Then the tool sees the setup cost at the slow corner when it inserts delay at the fast one. Prefer delay on paths with setup slack to spare at every corner. Fix shared skew in the clock tree before adding cells. A repair that must break setup to fix hold shows the constraints or the clock tree need work, not more cells.
Self-Check
Tick each key point you covered in your answer.
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Prove ItSolve L7.1.1: Make the Hold Repair Survive Four CornersSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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Break ItOne Delay Cell for Forty Hold FixesL2 Mid-LevelL3 Senior
Break it: the repair fixes forty hold violations with one delay cell on a shared net. What can go wrong?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
The shared net also feeds long paths, and they slow down by the same delay. With tight setup at the slow corner, those paths now fail. Put the delay near each failing D pin instead, where only the short path passes. Then check setup at every corner again.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"One cell for forty fixes is always the best repair."
It is the cheapest in area, but its delay lands on every path through that net. Paths with no setup margin then fail.
Source Lesson L5.5 key points
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Prove ItSolve L7.5.1: Reconnect the Selector Without New Base CellsSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Half-Truth
"The ECO fixed the two paths, so timing is closed."
An improved path is not multi-corner closure. Moved cells change neighbouring paths, and the fix must hold at every corner and mode.
Source ASIC Point lesson L7.5
Missed Corner
"The functional fix is one gate; simulation of the failing test is enough."
One test shows one point. Equivalence against the corrected RTL shows the whole function changed as intended and nothing else.
Source ASIC Point lesson L7.5 (Yosys equivalence of the exported netlist)