Fixing Setup Violations

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompare

1. Fixing Setup Violations
2. WhyWhy Wire Capacitance Hurts More Than Wire ResistanceL1 JuniorL2 Mid-Level

   On short nets, why does the wire's capacitance cost more delay than its resistance?

   Reveal the Model Answer

   The driving cell has to charge the wire's capacitance through its own output resistance, which is far larger than the wire's resistance. In lesson L4.5, 100 µm of met1 adds about 17 fF and 121 Ω, and an inv_1 driving it slows from 0.044 to 0.143 ns. The wire's own RC delay grows with length squared and only dominates on long nets.

   • input slew 0.01 ns
   • input slew 0.0388 ns
   • input slew 0.28 ns
   • input slew 1.5 ns

   1. Load 2.254 fFinput slew 0.01 ns = 20.7 ps · input slew 0.0388 ns = 30.3 ps · input slew 0.28 ns = 65.3 ps · input slew 1.5 ns = 83.7 ps

      The worked lookup: 2.254 fF at a 0.0388 ns slew gives 0.0303 ns.

   2. Load 100 fFinput slew 0.01 ns = 346.4 ps · input slew 0.0388 ns = 357.2 ps · input slew 0.28 ns = 451.5 ps · input slew 1.5 ns = 853.2 ps

      At 100 fF the fast input gives 0.3464 ns and the 1.5 ns input gives 0.8532 ns. The 1.5 ns input is slower than the 0.01 ns one at every load.

   3. Load 250 fFinput slew 0.01 ns = 845.4 ps · input slew 0.0388 ns = 855.8 ps · input slew 0.28 ns = 952.3 ps · input slew 1.5 ns = 1.496 ns

      At 0.25 pF the load is past the table's last column, 0.1813 pF. The tool extrapolates the last two columns in a straight line: 0.8558 ns.

   Read the plot as a table

   Load	input slew 0.01 ns	input slew 0.0388 ns	input slew 0.28 ns	input slew 1.5 ns
   1 fF	16.2 ps	24.9 ps	50.1 ps	48.1 ps
   2.254 fF	20.7 ps	30.3 ps	65.3 ps	83.7 ps
   10 fF	47.1 ps	57.7 ps	126.9 ps	233.4 ps
   100 fF	346.4 ps	357.2 ps	451.5 ps	853.2 ps
   250 fF	845.4 ps	855.8 ps	952.3 ps	1.496 ns

   Measured inv_1 delays: more load capacitance means more delay, at every input slew.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The driving cell has to charge the wire's capacitance through its own output resistance, which is far larger than the wire's resistance. Key point 2 In lesson L4.5, 100 µm of met1 adds about 17 fF and 121 Ω, and an inv_1 driving it slows from 0.044 to 0.143 ns. Key point 3 The wire's own RC delay grows with length squared and only dominates on long nets.

   • Lesson L4.5Timing-Driven Placement and the First Wire Delays
   • Lesson L6.4Wire RC and Parasitic Extraction
3. CompareTiming-Driven Placement vs Post-Placement RepairL2 Mid-Level

   Compare timing-driven placement with running repair_timing -setup on a placed design.

   Reveal the Model Answer

   Timing-driven placement re-weights the nets on critical paths while cells are still moving, so the fix costs little area. repair_timing works on fixed positions by resizing, buffering, swapping pins and cloning, which adds cells and needs another legalization. In lesson L4.5 the repair alone reached +0.056 ns while timing-driven placement reached +0.2145 ns on the same block.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Timing-driven placement re-weights the nets on critical paths while cells are still moving, so the fix costs little area. Key point 2 repair_timing works on fixed positions by resizing, buffering, swapping pins and cloning, which adds cells and needs another legalization. Key point 3 In lesson L4.5 the repair alone reached +0.056 ns while timing-driven placement reached +0.2145 ns on the same block.

   • Lesson L4.5Timing-Driven Placement and the First Wire Delays
4. Prove ItSolve L4.5.1: Close Placement Timing Within AreaSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L4.5.1

5. Break ItDesign-Rule Violations Before TimingL1 JuniorL2 Mid-Level

   Your timing looks fine, but 123 nets break max transition. Why does that matter, and what do you do first?

   Reveal the Model Answer

   Past the library's max transition or max capacitance, the delay tables are extrapolated. So the slack is a number the library never measured. Repair the design rules first, with buffer trees and stronger drivers, then trust the timing. In lesson L4.4 repair_design added six buffers and took 123 slew violations to zero.

   1. The port sees two pins

      The weak driver now loads only two buffer inputs and the wire to them.

   2. Each buffer sees its group

      Each buffer sits near its flops, so its wire is short and its load is within its limit.

   Read the diagram as text

   • rst_n port: Driven by a weak cell
   • Buffer: Near the first group
   • Buffer: Near the second group
   • Flops, group 1: RESET_B pins
   • Flops, group 2: RESET_B pins

   • rst_n port → Buffer
   • rst_n port → Buffer
   • Buffer → Flops, group 1
   • Buffer → Flops, group 2

   The shape only; repair_design chooses the number of buffers, their cells and their places.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Past the library's max transition or max capacitance, the delay tables are extrapolated. Key point 2 So the slack is a number the library never measured. Key point 3 Repair the design rules first, with buffer trees and stronger drivers, then trust the timing. Key point 4 In lesson L4.4 repair_design added six buffers and took 123 slew violations to zero.

   • Lesson L4.4Repairing Design Rules: Slew, Capacitance, Fanout
   • Lesson L2.2Delay and Slew from the Liberty Tables
   • Problem L4.4.1Repair the Slow Reset Tree
6. What IfWhen a Path Goes Back to RTLL3 Senior

   Asked if no physical fix closes the path

   A path still fails by 15 % of the period after every physical fix. What do you do?

   Reveal the Model Answer

   Stop spending flow iterations on it. Take it to the RTL owner with the evidence: the path, its logic depth and the best slack each fix reached. The structural options are pipelining, retiming, or restructuring the logic, each with a cost in latency or verification. Agree on it early, because an RTL change late in the schedule restarts synthesis, equivalence and the flow.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Stop spending flow iterations on it. Key point 2 Take it to the RTL owner with the evidence: the path, its logic depth and the best slack each fix reached. Key point 3 The structural options are pipelining, retiming, or restructuring the logic, each with a cost in latency or verification. Key point 4 Agree on it early, because an RTL change late in the schedule restarts synthesis, equivalence and the flow.

   • Lesson L4.5Timing-Driven Placement and the First Wire Delays
   • Lesson L1.3Your RTL in Real Cells
7. ComparePipelining Versus Retiming as the RTL FixL3 Senior

   Compare pipelining with retiming as the fix. What does each one cost the verification team?

   Reveal the Model Answer

   Pipelining adds a register stage, so latency grows by a cycle. Every interface, model and test that counts cycles must change. Retiming moves existing registers and keeps the latency at the ports. But the internal flops no longer match the RTL, so equivalence needs a sequential check.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Pipelining adds a register stage, so latency grows by a cycle. Key point 2 Every interface, model and test that counts cycles must change. Key point 3 Retiming moves existing registers and keeps the latency at the ports. Key point 4 But the internal flops no longer match the RTL, so equivalence needs a sequential check.

   Half-Truth

   "Retiming is free; the tool just does it."

   It changes which flops exist. Combinational equivalence cannot map them, and debug sees different internal state.

   • Lesson L8.4Capstone: RTL to a Reviewed Physical Handoff
   • Lesson F6.2SEC: Sequential Equivalence