Reading a Timing Report

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompareScale It

1. Reading a Timing Report
2. WhyThe Clock Reconvergence Pessimism LineL2 Mid-Level

   What is the "clock reconvergence pessimism" line, and why was it zero in that report?

   Reveal the Model Answer

   With on-chip-variation derates, the launch clock is timed late and the capture clock early. Where the two clock paths share buffers, one buffer cannot be both. So the tool credits back the difference on the shared part. With no derates and a single corner, late equals early and the credit is zero. In lesson L2.9, ±5 % derates gave a credit of 0.0138 ns.

   ffl → ffcsetup check, latest arrival3 cells

   • Clock latency
   • Cell delay
   • Setup time

   1. Late launch clock

      Through root and bl with the late derate: 0.2174 ns.

   2. Early capture clock, then the credit

      Through root and bc early: 0.1967 ns. The CRPR line adds 0.0138 ns, the two speeds of root.

   3. Slack

      0.5008 ns. Without the credit it would be 0.4870 ns.

   Read the path as a table

   Launch: clk rise edge at 0.0000 ns, clock latency 0.2174 ns. Capture: clk rise edge at 1.0000 ns, latency 0.1967 ns, library setup time −0.1040 ns.

   Arrival 0.6056 ns, required 1.1065 ns, slack 0.5008 ns (met).

   Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
   1	ffl/CLK → ffl/Q	dfxtp_1	fall	0.3094	0.5268	0.0345
   	ffl/Q → u1/A	wire q1	fall	0.0000	0.5268	0.0345
   2	u1/A → u1/Y	inv_1	rise	0.0438	0.5706	0.0308
   	u1/Y → u2/A	wire n1	rise	0.0000	0.5706	0.0308
   3	u2/A → u2/Y	nand2_1	fall	0.0350	0.6056	0.0251
   	u2/Y → ffc/D	wire n2	fall	0.0000	0.6056	0.0251

   The report

   Startpoint: ffl (rising edge-triggered flip-flop clocked by clk)
   Endpoint: ffc (rising edge-triggered flip-flop clocked by clk)
   Path Group: clk
   Path Type: max
   
   Fanout       Cap      Slew     Delay      Time   Description
   -------------------------------------------------------------------------------------
                                 0.0000    0.0000   clock clk (rise edge)
                                 0.0000    0.0000   clock source latency
        1    0.0022    0.1000    0.0000    0.0000 ^ clk (in)
                                                    clk (net)
                       0.1000    0.0000    0.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
        2    0.0044    0.0334    0.1450    0.1450 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                    cr (net)
                       0.0334    0.0000    0.1450 ^ bl/A (sky130_fd_sc_hd__clkbuf_1)
        1    0.0019    0.0353    0.0724    0.2174 ^ bl/X (sky130_fd_sc_hd__clkbuf_1)
                                                    cl (net)
                       0.0353    0.0000    0.2174 ^ ffl/CLK (sky130_fd_sc_hd__dfxtp_1)
        2    0.0044    0.0345    0.3094    0.5268 v ffl/Q (sky130_fd_sc_hd__dfxtp_1)
                                                    q1 (net)
                       0.0345    0.0000    0.5268 v u1/A (sky130_fd_sc_hd__inv_1)
        1    0.0024    0.0308    0.0438    0.5706 ^ u1/Y (sky130_fd_sc_hd__inv_1)
                                                    n1 (net)
                       0.0308    0.0000    0.5706 ^ u2/A (sky130_fd_sc_hd__nand2_1)
        1    0.0017    0.0251    0.0350    0.6056 v u2/Y (sky130_fd_sc_hd__nand2_1)
                                                    n2 (net)
                       0.0251    0.0000    0.6056 v ffc/D (sky130_fd_sc_hd__dfxtp_1)
                                           0.6056   data arrival time
   
                                 1.0000    1.0000   clock clk (rise edge)
                                 0.0000    1.0000   clock source latency
        1    0.0022    0.1000    0.0000    1.0000 ^ clk (in)
                                                    clk (net)
                       0.1000    0.0000    1.0000 ^ root/A (sky130_fd_sc_hd__clkbuf_4)
        2    0.0044    0.0334    0.1312    1.1312 ^ root/X (sky130_fd_sc_hd__clkbuf_4)
                                                    cr (net)
                       0.0334    0.0000    1.1312 ^ bc/A (sky130_fd_sc_hd__clkbuf_1)
        1    0.0019    0.0353    0.0655    1.1967 ^ bc/X (sky130_fd_sc_hd__clkbuf_1)
                                                    cc (net)
                       0.0353    0.0000    1.1967 ^ ffc/CLK (sky130_fd_sc_hd__dfxtp_1)
                                 0.0138    1.2105   clock reconvergence pessimism
                                -0.1040    1.1065   library setup time
                                           1.1065   data required time
   -------------------------------------------------------------------------------------
                                           1.1065   data required time
                                          -0.6056   data arrival time
   -------------------------------------------------------------------------------------
                                           0.5008   slack (MET)

   Setup with ±5 % derates. The CRPR line gives back 0.0138 ns for the clock buffers both paths share.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 With on-chip-variation derates, the launch clock is timed late and the capture clock early. Key point 2 Where the two clock paths share buffers, one buffer cannot be both. Key point 3 So the tool credits back the difference on the shared part. Key point 4 With no derates and a single corner, late equals early and the credit is zero. Key point 5 In lesson L2.9, ±5 % derates gave a credit of 0.0138 ns.

   • Lesson L2.9Corners, Derates, OCV and CPPR
3. CompareWNS, TNS and the Failing CountL1 Junior

   Compare WNS, TNS and the number of failing endpoints as measures of how bad a block's timing is.

   Reveal the Model Answer

   WNS is the worst endpoint's slack and says how hard the hardest path is. TNS sums the negative slacks and the failing count says how widespread the problem is. A WNS of -50 ps on two endpoints is a local fix. The same WNS on two thousand endpoints is a floorplan or constraint problem.

   1. Endpoint flop (ra, rb, p, acc) 0setup slack = 13.2 ps

      The input registers ra and rb load a and b but also obey en: slack 0.0132 ns.

   2. Endpoint flop (ra, rb, p, acc) 51setup slack = -468.8 ps

      The worst endpoint, acc[19]: -0.4688 ns. That is the WNS.

   3. Endpoint flop (ra, rb, p, acc) 51setup slack = -468.8 ps

      12 of 52 endpoints fail, in p and acc. Their negative slacks add up to about -2.172 ns: the TNS.

   Read the plot as a table

   Endpoint flop (ra, rb, p, acc)	setup slack
   0	13.2 ps
   10	13.2 ps
   20	-39 ps
   30	115 ps
   40	185.1 ps
   50	-435.9 ps
   51	-468.8 ps

   Setup slack at all 52 flops of lesson L2.5's MAC. The lowest point is the WNS; the failing points add up to the TNS.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 WNS is the worst endpoint's slack and says how hard the hardest path is. Key point 2 TNS sums the negative slacks and the failing count says how widespread the problem is. Key point 3 A WNS of -50 ps on two endpoints is a local fix. Key point 4 The same WNS on two thousand endpoints is a floorplan or constraint problem.

   • Lesson L2.5Reading a Timing Report
4. What IfA Clean Timing Report That Timed NothingL1 JuniorL2 Mid-Level

   Asked if they trust a clean report without asking what was timed

   A block's timing report says "No paths found." and TNS (total negative slack) is 0. The log has one warning, shown with the answer. Is the block clean?

   Reveal the Model Answer

   No: nothing was timed. The clock was declared on a port called clock, which does not exist. So no flop is clocked and no path has a constraint. Read every warning after loading the SDC and run check_setup, which lists unclocked registers and unconstrained endpoints. With the port name corrected, the same netlist reports a real slack of 3.837 ns.

   en → _827_setup check, latest arrival4 cells

   • Clock latency
   • Cell delay
   • Input delay
   • Uncertainty
   • Setup time

   1. Outside the block

      The SDC says en changes 4.5000 ns after the edge.

   2. The slowest gate

      a211oi_1 adds 0.4113 ns with a 0.4443 ns output slew.

   3. Required

      5 ns, minus 0.1 ns of uncertainty and a setup time of 0.0997 ns: 4.8003 ns.

   4. VIOLATED

      Slack = required − arrival = 4.8003 − 5.2691 = -0.4688 ns.

   Read the path as a table

   Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 5.0000 ns, latency 0.0000 ns, uncertainty −0.1000 ns, library setup time −0.0997 ns.

   Arrival 5.2691 ns, required 4.8003 ns, slack −0.4688 ns (violated).

   Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
   	en → _738_/B1	wire en	rise	0.0000	4.5000	0.0000
   1	_738_/B1 → _738_/Y	o21ai_0	fall	0.0722	4.5722	0.0807
   	_738_/Y → _740_/B1	wire _103_	fall	0.0000	4.5722	0.0807
   2	_740_/B1 → _740_/Y	a211oi_1	rise	0.4113	4.9834	0.4443
   	_740_/Y → _742_/C	wire _105_	rise	0.0000	4.9834	0.4443
   3	_742_/C → _742_/Y	nand3_1	fall	0.1474	5.1308	0.1058
   	_742_/Y → _748_/B	wire _107_	fall	0.0000	5.1308	0.1058
   4	_748_/B → _748_/Y	xnor2_1	fall	0.1383	5.2691	0.0405
   	_748_/Y → _827_/D	wire _048_	fall	0.0000	5.2691	0.0405

   The report

   Startpoint: en (input port clocked by clk)
   Endpoint: _827_ (rising edge-triggered flip-flop clocked by clk)
   Path Group: clk
   Path Type: max
   
   Fanout       Cap      Slew     Delay      Time   Description
   -------------------------------------------------------------------------------------
                       0.1000    0.0000    0.0000   clock clk (rise edge)
                                 0.0000    0.0000   clock network delay (ideal)
                                 4.5000    4.5000 ^ input external delay
       69    0.1868    0.0000    0.0000    4.5000 ^ en (in)
                                                    en (net)
                       0.0000    0.0000    4.5000 ^ _738_/B1 (sky130_fd_sc_hd__o21ai_0)
        2    0.0044    0.0807    0.0722    4.5722 v _738_/Y (sky130_fd_sc_hd__o21ai_0)
                                                    _103_ (net)
                       0.0807    0.0000    4.5722 v _740_/B1 (sky130_fd_sc_hd__a211oi_1)
        4    0.0119    0.4443    0.4113    4.9834 ^ _740_/Y (sky130_fd_sc_hd__a211oi_1)
                                                    _105_ (net)
                       0.4443    0.0000    4.9834 ^ _742_/C (sky130_fd_sc_hd__nand3_1)
        1    0.0045    0.1058    0.1474    5.1308 v _742_/Y (sky130_fd_sc_hd__nand3_1)
                                                    _107_ (net)
                       0.1058    0.0000    5.1308 v _748_/B (sky130_fd_sc_hd__xnor2_1)
        1    0.0019    0.0405    0.1383    5.2691 v _748_/Y (sky130_fd_sc_hd__xnor2_1)
                                                    _048_ (net)
                       0.0405    0.0000    5.2691 v _827_/D (sky130_fd_sc_hd__dfrtp_1)
                                           5.2691   data arrival time
   
                       0.1000    5.0000    5.0000   clock clk (rise edge)
                                 0.0000    5.0000   clock network delay (ideal)
                                -0.1000    4.9000   clock uncertainty
                                 0.0000    4.9000   clock reconvergence pessimism
                                           4.9000 ^ _827_/CLK (sky130_fd_sc_hd__dfrtp_1)
                                -0.0997    4.8003   library setup time
                                           4.8003   data required time
   -------------------------------------------------------------------------------------
                                           4.8003   data required time
                                          -5.2691   data arrival time
   -------------------------------------------------------------------------------------
                                          -0.4688   slack (VIOLATED)

   A path that a partial SDC never timed, in lesson L2.5. Once its input delay is in the SDC, it fails by 0.4688 ns.

   Warning 366: sdc line 1, port 'clock' not found.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 No: nothing was timed. Key point 2 The clock was declared on a port called clock, which does not exist. Key point 3 So no flop is clocked and no path has a constraint. Key point 4 Read every warning after loading the SDC and run check_setup, which lists unclocked registers and unconstrained endpoints. Key point 5 With the port name corrected, the same netlist reports a real slack of 3.837 ns.

   What Interviewers Listen For (Junior)

   A good junior answer suspects the constraints first. It finds the warning in the log and runs check_setup.

   Misconception

   "No violations means timing is met."

   A report lists only constrained paths. With the clock on a missing port it finds no paths at all. Correcting the port name gives a real check with 3.837 ns of slack.

   Run It

   The counter from lesson L1.6 with create_clock on a port named clock.

   create_clock -name clk -period 5 [get_ports clock]
   

   Prints: No paths found.

   See the Fix

   create_clock -name clk -period 5 [get_ports clk]
   

   Prints: 3.8370 slack (MET)

   Half-Truth

   "Warnings are noise; only errors matter."

   An ERROR stops the run, but a WARNING lets it finish, so a finished run can still be wrong. This one warning silently removed every clock.

   Source ASIC Point lesson L1.6 (OpenROAD message severities, measured log)

   • Lesson L1.6Reading a Flow Log
   • Lesson L2.5Reading a Timing Report
   • Problem L1.6.1The Clock That Reached No Register
   • Problem L1.6.2Reject an Incomplete Timing Report
5. WhyWhat check_setup CatchesL1 Junior

   Why run check_setup before reading any slack?

   Reveal the Model Answer

   It lists what the constraints leave out: unclocked register pins, inputs without input delays and outputs without output delays. It also lists unconstrained endpoints and combinational loops. In lesson L2.5 a partial SDC left two inputs and all twenty outputs without delays, so twenty endpoints were never timed. Each item is either fixed or explained before any slack counts.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 It lists what the constraints leave out: unclocked register pins, inputs without input delays and outputs without output delays. Key point 2 It also lists unconstrained endpoints and combinational loops. Key point 3 In lesson L2.5 a partial SDC left two inputs and all twenty outputs without delays, so twenty endpoints were never timed. Key point 4 Each item is either fixed or explained before any slack counts.

   • Lesson L2.5Reading a Timing Report
   • Lesson L2.7Input and Output Delays
   • Problem L1.6.1The Clock That Reached No Register
6. Prove ItSolve L1.6.1: The Clock That Reached No RegisterSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L1.6.1

7. Break ItA False Path That Swallowed Real PathsL1 JuniorL2 Mid-Level

   To silence one slow configuration input, someone writes the line below. What else disappears from timing?

   set_false_path -from [all_inputs]

   Reveal the Model Answer

   Every path from every input, including the clock-domain data inputs that really do need timing. In lesson L2.8 that line turned two flop data pins into unconstrained endpoints. A report through the data input then found no paths at all. Writing the exception on the one port, -from [get_ports cfg], left the other path timed with 0.5837 ns of slack.

   d0 → a0_regsetup check, latest arrival0 cells

   • Clock latency
   • Cell delay
   • Input delay
   • Setup time

   Read the path as a table

   Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 1.0000 ns, latency 0.0000 ns, library setup time −0.2163 ns.

   Arrival 0.2000 ns, required 0.7837 ns, slack 0.5837 ns (met).

   Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
   	d0 → a0_reg/D	wire d0	fall	0.0000	0.2000	0.0000

   The report

   Startpoint: d0 (input port clocked by clk)
   Endpoint: a0_reg (rising edge-triggered flip-flop clocked by clk)
   Path Group: clk
   Path Type: max
   
   Fanout       Cap      Slew     Delay      Time   Description
   -------------------------------------------------------------------------------------
                       0.1000    0.0000    0.0000   clock clk (rise edge)
                                 0.0000    0.0000   clock network delay (ideal)
                                 0.2000    0.2000 v input external delay
        1    0.0017    0.0000    0.0000    0.2000 v d0 (in)
                                                    d0 (net)
                       0.0000    0.0000    0.2000 v a0_reg/D (sky130_fd_sc_hd__edfxtp_1)
                                           0.2000   data arrival time
   
                       0.1000    1.0000    1.0000   clock clk (rise edge)
                                 0.0000    1.0000   clock network delay (ideal)
                                 0.0000    1.0000   clock reconvergence pessimism
                                           1.0000 ^ a0_reg/CLK (sky130_fd_sc_hd__edfxtp_1)
                                -0.2163    0.7837   library setup time
                                           0.7837   data required time
   -------------------------------------------------------------------------------------
                                           0.7837   data required time
                                          -0.2000   data arrival time
   -------------------------------------------------------------------------------------
                                           0.5837   slack (MET)

   With the exception written only on cfg, the path from d0 is timed again: slack 0.5837 ns.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Every path from every input, including the clock-domain data inputs that really do need timing. Key point 2 In lesson L2.8 that line turned two flop data pins into unconstrained endpoints. Key point 3 A report through the data input then found no paths at all. Key point 4 Writing the exception on the one port, -from [get_ports cfg], left the other path timed with 0.5837 ns of slack.

   • Lesson L2.8False Paths and Multicycle Paths
8. What IfA False Path That Covers the ResetL1 JuniorL2 Mid-Level

   What if the same broad false path also covers the reset input?

   Reveal the Model Answer

   Then the reset release has no recovery or removal check. A release near the clock edge can leave some flops in reset for one cycle longer than others. The design then starts in a mixed state. Time the release through its synchroniser, and keep recovery and removal checked.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Then the reset release has no recovery or removal check. Key point 2 A release near the clock edge can leave some flops in reset for one cycle longer than others. Key point 3 The design then starts in a mixed state. Key point 4 Time the release through its synchroniser, and keep recovery and removal checked.

   Misconception

   "Reset is asynchronous, so it needs no timing."

   Asserting it is asynchronous, but releasing it is checked against the clock by recovery and removal arcs.

   Source Lesson L2.1 key points

   • Lesson L2.8False Paths and Multicycle Paths
   • Lesson L2.1Timing Arcs: What a Cell Promises
9. Scale ItAuditing Constraints on a Large ChipL3 Senior

   You inherit SDC for a chip with forty clocks. How do you audit it before trusting any timing result?

   Reveal the Model Answer

   Check coverage first: every register clocked, every port with a delay, zero unexplained unconstrained endpoints. Then review every exception against a written reason, since a false path or clock group trusted by STA removes checks for good. Compare the clock relationships with the design spec and the CDC report. Re-run the audit whenever the SDC or the netlist changes.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Check coverage first: every register clocked, every port with a delay, zero unexplained unconstrained endpoints. Key point 2 Then review every exception against a written reason, since a false path or clock group trusted by STA removes checks for good. Key point 3 Compare the clock relationships with the design spec and the CDC report. Key point 4 Re-run the audit whenever the SDC or the netlist changes.

   • Lesson L7.1Sign-Off Timing: Every Corner, Every Check
   • Lesson L2.8False Paths and Multicycle Paths
   • Lesson L8.1Capstone: Constrain the Asynchronous FIFO
10. Prove ItSolve L1.6.2: Reject an Incomplete Timing ReportSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem L1.6.2

11. Scale ItAuditing Constraints on a Large ChipL3 Senior

    You inherit SDC for a chip with forty clocks. How do you audit it before trusting any timing result?

    Reveal the Model Answer

    Check coverage first: every register clocked, every port with a delay, zero unexplained unconstrained endpoints. Then review every exception against a written reason, since a false path or clock group trusted by STA removes checks for good. Compare the clock relationships with the design spec and the CDC report. Re-run the audit whenever the SDC or the netlist changes.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 Check coverage first: every register clocked, every port with a delay, zero unexplained unconstrained endpoints. Key point 2 Then review every exception against a written reason, since a false path or clock group trusted by STA removes checks for good. Key point 3 Compare the clock relationships with the design spec and the CDC report. Key point 4 Re-run the audit whenever the SDC or the netlist changes.

    • Lesson L7.1Sign-Off Timing: Every Corner, Every Check
    • Lesson L2.8False Paths and Multicycle Paths
    • Lesson L8.1Capstone: Constrain the Asynchronous FIFO