← Analog & Mixed-Signal Interviews
Interview Question · Concept
Intrinsic Gain and Channel Length
The Question
The interviewer asks
What is a transistor's intrinsic gain, and why does a longer channel raise it?
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Reveal the Model Answer
Intrinsic gain g_m·r_o is the most one transistor can give, with an ideal current-source load. It equals (g_m/I_D)·V_A, where g_m/I_D is transconductance per unit current. The Early voltage V_A grows with length, because the drain has less influence on a long channel. On sky130 at about 20 µA, V_A is 1.17 V at 0.15 µm and 22.8 V at 2 µm. So intrinsic gain rose from 16.7 to 131. Longer devices cost capacitance and speed.
- id_short
- id_long
- ro_short
- ro_long
- Drain-source voltage VDS 300 mVid_short = 13.03 µA · id_long = 20.7 µA · ro_short = 86.96 kΩ · ro_long = 79.86 kΩ
At 0.3 V the long device has only just saturated (its VDsat is 0.28 V), and ro is only 80 kΩ. The short one, past its 0.13 V VDsat, has 87 kΩ.
- Drain-source voltage VDS 900 mVid_short = 18.84 µA · id_long = 22.15 µA · ro_short = 109.7 kΩ · ro_long = 1.071 MΩ
At the operating point the long device's ro is 1.07 MΩ, almost ten times the short one's 110 kΩ, at about the same current.
- Drain-source voltage VDS 1.5 Vid_short = 24.23 µA · id_long = 22.63 µA · ro_short = 112.2 kΩ · ro_long = 1.38 MΩ
At 1.5 V the long device reaches 1.38 MΩ, while the short one stays near 112 kΩ. ro depends on VDS, so quote it at the operating point.
Read the plot as a table
| Drain-source voltage VDS | id_short | id_long | ro_short | ro_long |
|---|---|---|---|---|
| 0 V | 0 A | 0 A | 7.732 kΩ | 7.273 kΩ |
| 200 mV | 11.7 µA | 18.04 µA | 60.97 kΩ | 22.36 kΩ |
| 300 mV | 13.03 µA | 20.7 µA | 86.96 kΩ | 79.86 kΩ |
| 400 mV | 14.1 µA | 21.39 µA | 97.48 kΩ | 270 kΩ |
| 600 mV | 16.06 µA | 21.82 µA | 105.6 kΩ | 702.5 kΩ |
| 800 mV | 17.92 µA | 22.05 µA | 108.8 kΩ | 975.7 kΩ |
| 900 mV | 18.84 µA | 22.15 µA | 109.7 kΩ | 1.071 MΩ |
| 1 V | 19.75 µA | 22.24 µA | 110.4 kΩ | 1.149 MΩ |
| 1.2 V | 21.55 µA | 22.41 µA | 111.3 kΩ | 1.266 MΩ |
| 1.4 V | 23.34 µA | 22.56 µA | 112 kΩ | 1.349 MΩ |
| 1.5 V | 24.23 µA | 22.63 µA | 112.2 kΩ | 1.38 MΩ |
| 1.6 V | 25.13 µA | 22.71 µA | 112.3 kΩ | 1.403 MΩ |
| 1.8 V | 26.91 µA | 22.85 µA | 112.1 kΩ | 1.42 MΩ |
A short and a long sky130 device at about the same current. The long one has almost ten times the ro.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer defines g_m·r_o and links r_o to channel-length modulation. It says a longer device gives more gain.
What Interviewers Listen For (Senior)
A good senior answer compares lengths at a fixed g_m/I_D, so the gain-bandwidth stays the same. It measures r_o at the operating point, and weighs gain against speed.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItCompareScale It
- Intrinsic Gain and Channel Length
-
WhyReading the Early Voltage from a CurveL1 JuniorL2 Mid-Level
How do you extract the Early voltage and r_o from a simulated I_D-V_DS curve?
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Reveal the Model Answer
In saturation, take the slope of the curve, g_ds, at the operating point; r_o is its inverse. Extend the tangent back to zero current: it meets the V_DS axis at -V_A, so V_A = I_D/g_ds - V_DS and r_o ≈ V_A/I_D. Do it at the bias you will use, because both change with current and voltage.
DC sweepA 0.6/0.15 µm NMOS Against the λ = 0.1 V−1 ModelDrain current against drain voltage at VGS = 0.9 V. The dashed line is the textbook model through the same point at 0.9 V. Whole plot- id
- id_lambda
- Drain-source voltage VDS 900 mVid = 18.84 µA · id_lambda = 18.84 µA
The model and the device agree at the operating point, 18.8 µA at VDS = 0.9 V. Their slopes do not.
- Drain-source voltage VDS 1.8 Vid = 26.91 µA · id_lambda = 20.39 µA
At 1.8 V the device carries 26.9 µA; the λ = 0.1 V−1 line predicts 20.4 µA. The real slope is about five times steeper.
Read the plot as a table
Drain-source voltage VDS id id_lambda 0 V 0.000002267 fA 17.28 µA 200 mV 11.7 µA 17.63 µA 400 mV 14.1 µA 17.97 µA 600 mV 16.06 µA 18.32 µA 800 mV 17.92 µA 18.67 µA 900 mV 18.84 µA 18.84 µA 1 V 19.75 µA 19.01 µA 1.2 V 21.55 µA 19.36 µA 1.4 V 23.34 µA 19.7 µA 1.6 V 25.13 µA 20.05 µA 1.8 V 26.91 µA 20.39 µA A short device against the textbook λ model. The real slope, and so ro, must be read from the measured curve.
Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve E2.4.1: The Tail Current That Followed Its DrainSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
CompareThe Cascode and Its PriceL1 JuniorL2 Mid-Level
Your gain stage needs far more output resistance. You consider a cascode. What does it buy, and what does it cost?
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Reveal the Model Answer
A common-gate device on top holds the lower drain nearly still. The output resistance becomes about (g_m2 + g_mb2)·r_o2·r_o1, so the top device's intrinsic gain multiplies r_o1. In the lesson that was 71 times one device at the same output voltage. The price is headroom. The output must stay above the lower drain plus the top device's V_Dsat. On a 1.8 V supply, that is the real limit.
A Cascode Current SinkM1 sets the current from its gate voltage. M2, gate at VB, sits on M1's drain and passes the current up to the output. Whole circuit- One current through the stack
M1 sets 18.36 µA from its 0.75 V gate. M2 has no other path, so the same current flows through it and out of the output.
18.36 µA
- M2 holds node x
M2's gate is fixed at 1.2 V, and at a fixed current its VGS barely changes. So its source, node x, stays near 1.2 − 0.82 = 0.38 V.
- The output moves; x does not
Raise the output from 0.6 V to 1.2 V and node x moves only 6.8 mV, from 0.373 V to 0.380 V. M1 sees almost the same VDS, so its current hardly changes.
Read the circuit as text
- out port: terminal →
out - M2 NMOS transistor (W/L = 4/0.5): gate →
n1, drain →out, source →x - M1 NMOS transistor (W/L = 4/0.5): gate →
n2, drain →x, source →0 - VB voltage source (1.2 V): + →
n1, − →0 - VIN voltage source (0.75 V): + →
n2, − →0
out= 1.200 Vx= 0.380 V
Both bodies are at ground (the fourth node,
0). In the lab the output is held by VOUT and swept.DC sweepOutput Resistance Against Output VoltageRout = 1/(dI/dV) along the sweep, for one device and three cascode biases. Whole plot- one device
- V_B = 0.9 V
- V_B = 1.2 V
- V_B = 1.5 V
- Output voltage 400 mVone device = 293.4 kΩ · V_B = 0.9 V = 1.713 MΩ · V_B = 1.2 V = 427.7 kΩ · V_B = 1.5 V = 295.5 kΩ
At 0.4 V, M2 of the 1.2 V cascode is not yet saturated, and its Rout is still close to one device's.
- Output voltage 610.3 mVone device = 415.1 kΩ · V_B = 0.9 V = 3.598 MΩ · V_B = 1.2 V = 10 MΩ · V_B = 1.5 V = 561.2 kΩ
The VB = 1.2 V cascode passes 10 MΩ at 0.610 V, about 0.1 V above Vx + VDsat2.
- Output voltage 1.2 Vone device = 572 kΩ · V_B = 0.9 V = 6.338 MΩ · V_B = 1.2 V = 40.76 MΩ · V_B = 1.5 V = 47.44 MΩ
At 1.2 V: 0.57 MΩ for one device, 6.3 MΩ at VB = 0.9 V, 40.8 MΩ at 1.2 V and 47.4 MΩ at 1.5 V.
Read the plot as a table
Output voltage one device V_B = 0.9 V V_B = 1.2 V V_B = 1.5 V 0 V 4.257 kΩ 6.11 kΩ 5.152 kΩ 4.884 kΩ 200 mV 96.53 kΩ 65.35 kΩ 75.91 kΩ 82.97 kΩ 400 mV 293.4 kΩ 1.713 MΩ 427.7 kΩ 295.5 kΩ 600 mV 410.5 kΩ 3.524 MΩ 9.075 MΩ 536 kΩ 610.3 mV 415.1 kΩ 3.598 MΩ 10 MΩ 561.2 kΩ 800 mV 485.1 kΩ 4.747 MΩ 24.29 MΩ 6.528 MΩ 1 V 536 kΩ 5.642 MΩ 34.07 MΩ 31 MΩ 1.2 V 572 kΩ 6.338 MΩ 40.76 MΩ 47.44 MΩ 1.4 V 597 kΩ 6.86 MΩ 45.56 MΩ 58.36 MΩ 1.6 V 609.9 kΩ 7.023 MΩ 47.68 MΩ 66.08 MΩ 1.8 V 605.4 kΩ 6.412 MΩ 40.83 MΩ 70.13 MΩ Measured output resistance. Once the top device saturates, the cascode is about 71 times one device at 1.2 V.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer states how much the cascode raises the output resistance. It also names the price: one more V_Dsat of headroom.
What Interviewers Listen For (Senior)
A good senior answer sets the cascode bias at V_GS2 plus V_Dsat1 plus a margin, and checks the swing at every corner. It compares the cascode with a longer single device or a gain-boosted cascode.
Half-Truth
"Cascode everything for gain; it is free."
Each cascode costs about one V_Dsat plus a margin of swing. On a 1.8 V supply a cascoded output and a cascoded load leave little room for the signal.
Source ASIC Point lesson E3.7
Missed Corner
"Bias the cascode gate anywhere above the input."
Too low and the lower device leaves saturation; too high and the swing shrinks. The bias must be about V_GS2 plus V_Dsat1, with a margin, and checked across corners.
Source ASIC Point lesson E3.7
- One current through the stack
-
WhyWhy the Cascode Multiplies r_oL1 JuniorL2 Mid-Level
Explain in words why a cascode's output resistance is about g_m·r_o times larger than one device's.
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Reveal the Model Answer
Push the output up by a volt. The top device's r_o lets a little extra current flow, which raises the voltage at the lower drain, its source. That rise turns the top device down by g_m times the rise, cancelling most of the extra current. The output must move about g_m·r_o times further for the same current change.
DC sweepOutput Current Against Output VoltageOne NMOS and the cascode, both with the input gate at 0.75 V. A flat curve means a high output resistance. Whole plot- one device
- cascode, V_B = 1.2 V
- Output voltage 300 mVone device = 18.03 µA · cascode, V_B = 1.2 V = 17.82 µA
At low voltage both sinks are still rising. The single device is already saturated; the cascode is not.
- Output voltage 1.2 Vone device = 20.19 µA · cascode, V_B = 1.2 V = 18.36 µA
At 1.2 V the single device's current still climbs with the output: 0.572 MΩ. The cascode's line is almost flat: 40.8 MΩ.
Read the plot as a table
Output voltage one device cascode, V_B = 1.2 V 0 V 0 A 0.000003521 fA 200 mV 17.35 µA 17.04 µA 300 mV 18.03 µA 17.82 µA 400 mV 18.43 µA 18.17 µA 600 mV 19 µA 18.33 µA 800 mV 19.44 µA 18.35 µA 1 V 19.83 µA 18.35 µA 1.2 V 20.19 µA 18.36 µA 1.4 V 20.53 µA 18.36 µA 1.6 V 20.87 µA 18.37 µA 1.8 V 21.19 µA 18.37 µA The same sinks as current against output voltage. The cascode line is almost flat: a high output resistance.
Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve E3.7.1: The Smallest Cascode SinkSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
CompareSimple Mirror vs Cascode MirrorL1 JuniorL2 Mid-Level
Compare a simple mirror with a cascode mirror.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A cascode device on top raises the output resistance by about (g_m + g_mb)·r_o. In the lesson it went from 0.80 MΩ to 102 MΩ. The price is headroom: the output now needs about V_GS + V_Dsat, around 0.85 V. A wide-swing version gets most of the gain back while the output can fall to about 0.3 V.
Self-Check
Tick each key point you covered in your answer.
-
Scale ItDesigning a Wide-Swing Cascode MirrorL2 Mid-LevelL3 Senior
A differential pair's tail must stay accurate down to a low output voltage. You choose a wide-swing cascode mirror. How do you size its bias, and how do you check it?
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Reveal the Model Answer
A separate diode device biases the cascode gates. It is sized so the bottom devices sit just above V_Dsat. The textbook W/4 rule comes from the square law, and in sky130 it left the copy 12 % low. A cascode on the reference side makes both bottom devices see the same V_DS and fixes the copy. Then sweep the output to find where the current is 1 % low, at every corner.
A Wide-Swing Mirror with a Reference-Side CascodeXB sets the bias line b. R2 and O2 are cascodes on it; R1 and O1 share the gate node g, the top of the reference branch. Whole circuit- The bias device sets b
XB is an eighth of the 8 µm width. At 20 µA it needs a larger VGS, so the bias line b sits at 1.014 V.
20 µA
- The cascodes hold y and x low
R2 and O2 have their gates on b, so their sources sit one VGS lower: y = 0.245 V and x = 0.246 V. Both bottom devices get about 0.25 V, above their 0.137 V VDsat.
- The bottom devices match
R1's gate is tied to g, the top of the reference branch, so g settles where R1 carries 20 µA at y. O1 shares g and sits at nearly the same VDS: it copies 20.006 µA at 0.9 V.
20.006 µA
- Room at the output
O2 needs only its own VDsat above x, so the output can fall to 0.297 V before the current is 1 % low.
Read the circuit as text
- IB current source (20 µA): + →
VDD, − →b - XB NMOS transistor (1/1): gate →
b, drain →b, source →0 - IREF current source (20 µA): + →
VDD, − →g - R2 NMOS transistor (8/1): gate →
b, drain →g, source →y - R1 NMOS transistor (8/1): gate →
g, drain →y, source →0 - O2 NMOS transistor (8/1): gate →
b, drain →n1, source →x - O1 NMOS transistor (8/1): gate →
g, drain →x, source →0 - out port: terminal →
n1
b= 1.014 Vg= 0.718 Vy= 0.245 Vx= 0.246 V
Node voltages at Vout = 0.9 V from the lab's mirror m8. Widths in µm, all L = 1 µm; all bodies are the substrate at ground.
DC sweepFour 20 µA Mirrors Against Output VoltageSimple (i_s), stacked cascode (i_c), wide-swing by the W/4 rule (i_w4), and wide-swing with a reference-side cascode and a W/8 bias device (i_m8). Whole plot- i_s
- i_c
- i_w4
- i_m8
- Output voltage VO 300 mVi_s = 19.16 µA · i_c = 19.11 µA · i_w4 = 17.37 µA · i_m8 = 19.81 µA
At 0.3 V the matched W/8 mirror already gives 19.81 µA. The simple and the stacked mirrors give about 19.1 µA, the W/4 mirror 17.4 µA.
- Output voltage VO 900 mVi_s = 20.27 µA · i_c = 19.99 µA · i_w4 = 17.55 µA · i_m8 = 20.01 µA
At 0.9 V: simple 20.27 µA, stacked 19.99 µA, W/4 17.55 µA, matched W/8 20.006 µA.
- Output voltage VO 1.7 Vi_s = 21.26 µA · i_c = 20 µA · i_w4 = 17.64 µA · i_m8 = 20.02 µA
At 1.7 V the simple mirror has climbed to 21.26 µA; the cascodes have hardly moved.
Read the plot as a table
Output voltage VO i_s i_c i_w4 i_m8 0 V 0 A 0 A 0 A 0 A 200 mV 18.64 µA 18.51 µA 16.67 µA 19 µA 300 mV 19.16 µA 19.11 µA 17.37 µA 19.81 µA 400 mV 19.44 µA 19.39 µA 17.45 µA 19.97 µA 600 mV 19.82 µA 19.76 µA 17.5 µA 20 µA 800 mV 20.13 µA 19.97 µA 17.53 µA 20 µA 900 mV 20.27 µA 19.99 µA 17.55 µA 20.01 µA 1 V 20.4 µA 19.99 µA 17.56 µA 20.01 µA 1.2 V 20.66 µA 20 µA 17.58 µA 20.01 µA 1.4 V 20.9 µA 20 µA 17.61 µA 20.02 µA 1.6 V 21.14 µA 20 µA 17.63 µA 20.02 µA 1.7 V 21.26 µA 20 µA 17.64 µA 20.02 µA 1.8 V 21.38 µA 20 µA 17.65 µA 20.03 µA Four 20 µA mirrors swept. The W/4 mirror is flat but 12 % low; the matched W/8 mirror is right and works down to about 0.3 V.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains how the extra diode device sets the cascode bias. It checks the copy and the lowest output voltage by sweeping the output.
What Interviewers Listen For (Senior)
A good senior answer uses the bias width to trade output resistance against the lowest output voltage. It adds a reference-side cascode for accuracy, and checks every corner.
Half-Truth
"Use the W/4 rule for the bias device and you are done."
The rule comes from the square law. In sky130 it left the copy 12 % low. Find the bias width by sweeping, not from the ratio.
Source ASIC Point lesson E4.3 (measured)
Buzzword Without Mechanism
"The minimum output voltage is two V_Dsat."
That is a hand estimate. The lesson defines it as the voltage where the current falls 1 % below its value at 0.9 V, and measures it.
Source ASIC Point lessons E4.1 and E4.3
- The bias device sets b
-
WhyWhy a Reference-Side Cascode Fixes the CopyL2 Mid-Level
Why does adding a cascode on the reference side make the wide-swing copy accurate?
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Reveal the Model Answer
In the plain wide-swing mirror the reference device is diode-connected, so its V_DS is V_GS. The output's bottom device sits near V_Dsat instead. Different V_DS means a different current. A cascode on the reference side holds its bottom device at the same low V_DS as the output side. Then both carry the same current.
DC sweepA Wide-Swing Mirror Sized by the W/4 RuleOutput current against output voltage. Every device is W/L = 8/1 µm except the 2/1 µm bias device. Whole plot- Output voltage VO 900 mVi_w4 = 17.55 µA
At 0.9 V the copy is 17.55 µA: a flat curve, at the wrong current.
- Output voltage VO 1.7 Vi_w4 = 17.64 µA
At 1.7 V it is still only 17.64 µA. A high output resistance holds an error as faithfully as a correct current.
Read the plot as a table
Output voltage VO i_w4 0 V 0 A 200 mV 16.67 µA 400 mV 17.45 µA 600 mV 17.5 µA 800 mV 17.53 µA 900 mV 17.55 µA 1 V 17.56 µA 1.2 V 17.58 µA 1.4 V 17.61 µA 1.6 V 17.63 µA 1.7 V 17.64 µA 1.8 V 17.65 µA The wide-swing mirror without a reference-side cascode: a flat curve at the wrong current, 17.55 µA instead of 20 µA.
Self-Check
Tick each key point you covered in your answer.
- Output voltage VO 900 mVi_w4 = 17.55 µA
-
Prove ItSolve E4.3.1: The Leanest Wide-Swing SinkSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
What IfSizing the Wide-Swing Bias by the Square LawL2 Mid-LevelL3 Senior
What if you size the cascode bias device by the square-law W/4 rule instead of sweeping? What happens in sky130?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
In the lesson the W/4 rule left the copy 12 % low. Short sky130 devices do not follow the square law, so the bottom devices end up at the wrong V_DS. The bias width trades output resistance against the lowest output voltage. So find it by sweeping, and check the copy at the target output range.
Self-Check
Tick each key point you covered in your answer.
Misconception
"W/4 is exact; the textbook derives it."
The derivation assumes the square law. Short devices break that model, so the derived width puts the bottom devices at the wrong voltage.
Source Lesson E4.3 key points
-
CompareSimple Mirror vs Cascode MirrorL1 JuniorL2 Mid-Level
Compare a simple mirror with a cascode mirror.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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Reveal the Model Answer
A cascode device on top raises the output resistance by about (g_m + g_mb)·r_o. In the lesson it went from 0.80 MΩ to 102 MΩ. The price is headroom: the output now needs about V_GS + V_Dsat, around 0.85 V. A wide-swing version gets most of the gain back while the output can fall to about 0.3 V.
Self-Check
Tick each key point you covered in your answer.
-
Scale ItWriting a Bias Block SpecificationL3 Senior
You must hand over a bias block to other designers. How do you write its specification and prove it?
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Reveal the Model Answer
Write each requirement as one line with a limit and a measurement, set after measuring a reference design at every corner. Use one bench per check. Run a supply sweep and a temperature and supply sweep for the worst case. Add an output sweep for compliance and power-up transients, fast and slow. A constant-g_m reference moves its current on purpose, so specify the tail current as a band.
The Bias Block, Piece by PieceArrows show where a current or a gate voltage goes. W/L in µm. Illustrative sequence- Reference and start-up
The beta multiplier of E4.4 sets 10 µA with a
res_high_poresistor (W = 0.35 µm, L = 8.54 µm). The start-up of E4.5 kicks it on at power-up and then switches off. - Send currents
PMOS devices on the reference's gate line b copy its current: 10 µA for the NMOS reference stack and 2.5 µA for the cascode bias. Currents travel; gate voltages stay local (E4.2).
- Wide-swing cascode
The 2.5 µA diode XBC sets the cascode gate c. The reference stack sets the bottom gate g with its own cascode, so both bottom devices see the same drain voltage (E4.3). The tail is two units of the stack: 20 µA.
- PMOS bias output
One more unit on gate g sinks 10 µA from a diode-connected 8/1 PMOS. Its gate is
pbias: any 8/1 PMOS with its source at VDD and this gate voltage sources about 10 µA.
Read the diagram as text
- Start-up: XS1-XS3: kick at power-up, then off
- Reference: Beta multiplier, K = 4, RS a res_high_po: 10 µA
- PMOS copies: XP3 4/1: 10 µA; XP4 1/1: 2.5 µA
- Cascode bias: XBC 0.5/1.5 diode sets node c
- Reference stack: XC1 over XB1, 16/1 units: node g
- Tail output: XC2 over XB2, two units: 20 µA
- PMOS bias output: XB3 sinks 10 µA from XPB 8/1
- Start-up → Reference: kick
- Reference → PMOS copies: gate b
- PMOS copies → Cascode bias: 2.5 µA
- PMOS copies → Reference stack: 10 µA
- Cascode bias → Tail output: gate c
- Reference stack → Tail output: gate g
- Reference stack → PMOS bias output: gate g
The full netlist is the Try it below. Units are whole devices (
m=2for the tail), so the 2:1 ratio does not depend on drawn widths matching.Self-Check
Tick each key point you covered in your answer.
- Reference and start-up
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Prove ItSolve E3.3.1: A Gain of 120 into 2 pFSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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What IfWhy Gain Is Bought with VoltageL1 JuniorL2 Mid-Level
Why does a resistor-loaded stage's gain depend on the voltage across the resistor rather than the bias current?
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Reveal the Model Answer
g_m·R_D can be written as (g_m/I_D)·(I_D·R_D), and I_D·R_D is just the DC drop across the load. For a given g_m/I_D, more current with a proportionally smaller R_D gives the same gain. The supply limits that drop, which is why high-gain stages use current-source loads instead of resistors.
Self-Check
Tick each key point you covered in your answer.
What People Get Wrong
Common wrong answers and why they fail.
Spec Misquote
"Use λ = 0.1 per volt from the textbook to get r_o."
λ is a fit for one length at one bias. On sky130 the Early voltage changes about twentyfold between 0.15 µm and 2 µm, so measure r_o at your operating point.
Source ASIC Point lesson E2.4 (measured)
Half-Truth
"A longer device always makes the amplifier slower."
At a fixed g_m/I_D and load, the unity-gain frequency g_m/(2πC_L) stays the same while gain rises. What falls is the device's own transit frequency and the speed of internal nodes.
Source ASIC Point lesson E3.3