Interview Question · Debug

Systematic and Random Offset

L1 JuniorL2 Mid-Leveloffsetop amp

Likely at Texas Instruments

The interviewer asks

Your OTA, wired as a unity-gain buffer with no mismatch, shows the result below. Where does this offset come from, and what other offset will silicon add?

log

OTA-A as a unity-gain buffer, no mismatch (lesson E5.4, measured)
vos      = -2.165886e-03 V   (vout - vin)
vos_hand = -2.042426e-03 V   (-(vout - vx)/A0)

Reveal the Model Answer

This is systematic offset, built into the schematic. In a 5T OTA the output and the diode node sit at different voltages. So the two halves are not in the same state. The offset is about -(V_out - V_x)/A_0, -2.04 mV by hand against -2.17 mV measured. Silicon adds random offset from device mismatch, different on every chip. It shrinks with device area.

DC sweepThe Offset Vanishes Where the Drains MatchAbove: the buffer's error. Below: the gap between the output and node x.

v(out) − v(in)
v(out) − v(x)

Input 675.1 mVv(out) − v(in) = -33.11 pV · v(out) − v(x) = 15.41 nV
At an input of 0.675 V the output sits exactly at V_x: both halves see the same voltages, and the error is zero at the same point.
Input 900 mVv(out) − v(in) = -2.166 mV · v(out) − v(x) = 280 mV
At 0.9 V the gap is 0.280 V and the error −2.17 mV.
Input 1.2 Vv(out) − v(in) = -6.221 mV · v(out) − v(x) = 581.2 mV
Higher up the gap and the error both grow.

Read the plot as a table

Input	v(out) − v(in)	v(out) − v(x)
600 mV	982.8 µV	-131.9 mV
675.1 mV	-33.11 pV	15.41 nV
700 mV	-280.3 µV	38.96 mV
800 mV	-1.279 mV	172.4 mV
900 mV	-2.166 mV	280 mV
1 V	-3.114 mV	381.6 mV
1.1 V	-4.277 mV	481.9 mV
1.2 V	-6.221 mV	581.2 mV

The systematic offset is zero only where the output sits at the level of node x. At 0.9 V the error is -2.17 mV.

The offset bench from lesson E5.4.

SPICEngspice 42 · simulator service

Edit the netlist, then run it

Expected: vos = -2.165886e-03 vos_hand = -2.042426e-03

* E5.4 lab: OTA-A as a unity-gain buffer, with and without 1 mV of mismatch at one gate
.lib sky130 tt
* OTA-A with a series source at each gate: d1..d4 model a threshold error of M1..M4
.subckt otam inp inn out vdd d1=0 d2=0 d3=0 d4=0
IB vdd nb 20u
XMB nb nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
XM5 tail nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
V1 g1 inp {d1}
V2 g2 inn {d2}
V3 g3 x {d3}
V4 g4 x {d4}
XM1 x g1 tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
XM2 out g2 tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
XM3 x g3 vdd vdd sky130_fd_pr__pfet_01v8 W=8 L=1
XM4 out g4 vdd vdd sky130_fd_pr__pfet_01v8 W=8 L=1
.ends
VDD vdd 0 1.8
VIN in 0 0.9
* buffers: the output drives the - input
X0 in o0 o0 vdd otam
X1 in o1 o1 vdd otam d1=1m
X2 in o2 o2 vdd otam d2=1m
X3 in o3 o3 vdd otam d3=1m
X4 in o4 o4 vdd otam d4=1m
* no feedback: both inputs on the same 0.9 V
XT in in ot vdd otam
.control
op
let gm1=@m.x0.xm1.msky130_fd_pr__nfet_01v8[gm]
let gm2=@m.x0.xm2.msky130_fd_pr__nfet_01v8[gm]
let gm3=@m.x0.xm3.msky130_fd_pr__pfet_01v8[gm]
let gm4=@m.x0.xm4.msky130_fd_pr__pfet_01v8[gm]
let a0=gm2/(@m.x0.xm2.msky130_fd_pr__nfet_01v8[gds]+@m.x0.xm4.msky130_fd_pr__pfet_01v8[gds])
let vxo=v(x0.x)
let i3=@m.x0.xm3.msky130_fd_pr__pfet_01v8[id]
let i4=@m.x0.xm4.msky130_fd_pr__pfet_01v8[id]
* sweep the input; every buffer follows it
dc VIN 0.6 1.25 0.001
let e0=v(o0)-v(in)
let e2=v(o2)-v(in)
let s1=v(o1)-v(o0)
let s2=v(o2)-v(o0)
let s3=v(o3)-v(o0)
let s4=v(o4)-v(o0)
let gap=v(o0)-v(x0.x)
let one=1+0*v(in)
let a0x=op1.a0*one
let eh=-(v(o0)-op1.vxo)/op1.a0*one
let r3=op1.gm3/op1.gm1*one
let r4=op1.gm4/op1.gm2*one
let rs=sqrt(s1*s1+s2*s2+s3*s3+s4*s4)
let vxx=op1.vxo*one
let i3x=op1.i3*one
let i4x=op1.i4*one
meas dc vos FIND e0 AT=0.9
meas dc vx FIND vxx AT=0.9
meas dc a0 FIND a0x AT=0.9
meas dc vos_hand FIND eh AT=0.9
meas dc i3 FIND i3x AT=0.9
meas dc i4 FIND i4x AT=0.9
meas dc shift_m1 FIND s1 AT=0.9
meas dc shift_m2 FIND s2 AT=0.9
meas dc shift_m3 FIND s3 AT=0.9
meas dc shift_m4 FIND s4 AT=0.9
meas dc k3 FIND r3 AT=0.9
meas dc k4 FIND r4 AT=0.9
meas dc rss FIND rs AT=0.9
meas dc vos_m2 FIND e2 AT=0.9
meas dc open_loop FIND v(ot) AT=0.9
meas dc vin_zero WHEN e0=0
meas dc gap_zero WHEN gap=0
.endc
.end

Self-Check

Tick each key point you covered in your answer.

Key point 1 This is systematic offset, built into the schematic. Key point 2 In a 5T OTA the output and the diode node sit at different voltages. Key point 3 So the two halves are not in the same state. Key point 4 The offset is about -(V_out - V_x)/A_0, -2.04 mV by hand against -2.17 mV measured. Key point 5 Silicon adds random offset from device mismatch, different on every chip. Key point 6 It shrinks with device area.

What Interviewers Listen For (Junior)

A good junior answer separates systematic offset, which comes from the design, from random offset, which is different on every chip.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompare

Systematic and Random Offset
WhyWhy the Load Mirror Adds OffsetL2 Mid-Level
Why does a threshold error in the PMOS load show up at the input scaled by g_m,load/g_m,pair?

Reveal the Model Answer

A threshold error ΔV in a load device changes its current by g_m,load·ΔV. To cancel that current, the input pair needs a differential input that changes its current by the same amount. That input is g_m,load·ΔV divided by g_m,pair. So the load's error reaches the input scaled by the ratio of the two transconductances.

Self-Check
Tick each key point you covered in your answer.
Key point 1 A threshold error ΔV in a load device changes its current by g_m,load·ΔV. Key point 2 To cancel that current, the input pair needs a differential input that changes its current by the same amount. Key point 3 That input is g_m,load·ΔV divided by g_m,pair. Key point 4 So the load's error reaches the input scaled by the ratio of the two transconductances.
- Lesson E5.4Offset: Systematic and Random
- Problem E5.5.1The Offset That Came with a Faster Edge
Prove ItSolve E5.5.1: The Offset That Came with a Faster EdgeSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem E5.5.1
CompareMonte Carlo on an Amplifier's OffsetL1 JuniorL2 Mid-Level
Set up a Monte Carlo run for an OTA's offset. What do you report from it, and what number do you sign off?
2:30

You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.

Your level

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Reveal the Model Answer

Give every transistor in every copy its own random draw. In sky130, turn mismatch on with MC_MM_SWITCH=1 and fix the seed, so the run repeats. Report the mean and σ. The mean is the systematic offset plus a small sampling error. Sign off at the mean plus or minus 3σ, not at the worst die you happened to sample. In the lesson 30 dies gave a mean of -2.62 mV and σ of 1.83 mV.

One Die: OTA-A as a FollowerThe output drives M2's gate, so the output follows the input. Every transistor draws its own threshold shift.

The input pair
A threshold shift of M2 against M1 appears at the input one to one.
The load mirror
A shift of M4 against M3 changes M4's current by g_m3ΔV. M2 must absorb it, so the input sees ΔV·g_m3/g_m1, 0.57 times the shift.
The bias
MB and M5 change the tail current, which both halves share: what is left after the pair and load parts spreads by 24 µV.

Read the circuit as text
M3 PMOS transistor (load 8/1): gate → n1, source → VDD, drain → n1
M4 PMOS transistor (load 8/1): gate → n1, source → VDD, drain → n2
M1 NMOS transistor (pair 10/1): gate → n3, drain → n1, source → n4
M2 NMOS transistor (pair 10/1): gate → n2, drain → n2, source → n4
IB current source (20 µA): + → VDD, − → n5
MB NMOS transistor (8/1): gate → n5, drain → n5, source → 0
M5 NMOS transistor (8/1): gate → n5, drain → n4, source → 0
out port: terminal → n2
in port: terminal → n3

OTA-A of E5.3 (W/L in µm). In SKY130 the mismatch model shifts the threshold of each transistor only.

HistogramOffset of 30 OTA-A Followers, Pair 10/1, Load 8/1Offset = output − input, at 0.9 V in.

Read the histogram as a table
Offset from to Dies
-9 mV -8 mV 0
-8 mV -7 mV 0
-7 mV -6 mV 0
-6 mV -5 mV 3
-5 mV -4 mV 5
-4 mV -3 mV 5
-3 mV -2 mV 6
-2 mV -1 mV 7
-1 mV 0 V 2
0 V 1 mV 1
1 mV 2 mV 0
2 mV 3 mV 0
3 mV 4 mV 1
30 values in 13 bins.

Offset of 30 Monte Carlo dies, seed 5: mean -2.62 mV, σ 1.83 mV.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Give every transistor in every copy its own random draw. Key point 2 In sky130, turn mismatch on with MC_MM_SWITCH=1 and fix the seed, so the run repeats. Key point 3 Report the mean and σ. Key point 4 The mean is the systematic offset plus a small sampling error. Key point 5 Sign off at the mean plus or minus 3σ, not at the worst die you happened to sample. Key point 6 In the lesson 30 dies gave a mean of -2.62 mV and σ of 1.83 mV.

What Interviewers Listen For (Junior)
A good junior answer turns mismatch on with a fixed seed, so the run repeats. It reports the mean and σ of the offset.
Misconception

"Sign off at the worst die in the Monte Carlo run."

The worst of 30 samples depends on luck. The lesson's worst sampled die was -5.19 mV, while mean minus 3σ is about -8.1 mV. Use the statistics, not the sample.

Source ASIC Point lesson E7.5 (measured)

Half-Truth

"Thirty samples give an exact σ."

Thirty samples know σ only to about ±13 %. Add margin, or run more samples, before trusting a tight budget.

Source ASIC Point lesson E7.4

Offset from	to	Dies
-9 mV	-8 mV	0
-8 mV	-7 mV	0
-7 mV	-6 mV	0
-6 mV	-5 mV	3
-5 mV	-4 mV	5
-4 mV	-3 mV	5
-3 mV	-2 mV	6
-2 mV	-1 mV	7
-1 mV	0 V	2
0 V	1 mV	1
1 mV	2 mV	0
2 mV	3 mV	0
3 mV	4 mV	1

WhyPelgrom's LawL1 JuniorL2 Mid-Level

Why does a bigger device match better, and by how much?

Reveal the Model Answer

Random variations in doping and edges average out over a larger gate. For a pair, σ of the threshold difference is A_VT divided by √(W·L). Four times the area halves it. For sky130 the lesson found A_VT of about 4.75 mV·µm for the NMOS and 8.28 mV·µm for the PMOS.

DC sweepThreshold Mismatch of a Pair Against 1/√(W·L)The straight line is Pelgrom's law with A_VT = 4.746 mV·µm. The curve adds the model's size factor for square devices. The points are 20 measured pairs at each size.

Pelgrom, 4.746 mV·µm
model, square devices

1/sqrt(W·L) (1/µm) 0.25Pelgrom, 4.746 mV·µm = 1.187 mV · model, square devices = 1.23 mV
The 4/4 pairs, 16 µm²: 1.131 mV measured, 1.230 mV on the model curve.
1/sqrt(W·L) (1/µm) 0.5Pelgrom, 4.746 mV·µm = 2.373 mV · model, square devices = 2.677 mV
The 2/2 pairs, 4 µm²: 2.895 mV measured against 2.677 mV on the curve. A quarter of the area, about twice the mismatch.
1/sqrt(W·L) (1/µm) 1Pelgrom, 4.746 mV·µm = 4.746 mV · model, square devices = 6.398 mV
The 1/1 pairs, 1 µm²: the model curve is 6.398 mV, 35 % above the straight line's 4.746 mV. That is the model's size factor. The 20 pairs measure 5.103 mV.

Read the plot as a table

1/sqrt(W·L) (1/µm)	Pelgrom, 4.746 mV·µm	model, square devices
0.2	949.2 µV	968.3 µV
0.25	1.187 mV	1.23 mV
0.3	1.424 mV	1.501 mV
0.4	1.898 mV	2.07 mV
0.5	2.373 mV	2.677 mV
0.6	2.848 mV	3.325 mV
0.7	3.322 mV	4.018 mV
0.8	3.797 mV	4.759 mV
0.9	4.271 mV	5.551 mV
1	4.746 mV	6.398 mV

Measured on ngspice 42 with 20 pairs per size and seed 5. The 10/1 device is not square, so it sits near the line and off the curve.

Self-Check

Tick each key point you covered in your answer.

Key point 1 Random variations in doping and edges average out over a larger gate. Key point 2 For a pair, σ of the threshold difference is A_VT divided by √(W·L). Key point 3 Four times the area halves it. Key point 4 For sky130 the lesson found A_VT of about 4.75 mV·µm for the NMOS and 8.28 mV·µm for the PMOS.

Prove ItSolve E7.5.1: Offset by the Square MicrometreSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem E7.5.1
WhyWhy Mismatch Falls as the Square Root of AreaL2 Mid-Level
Why does mismatch fall with 1/√(W·L), and not with 1/(W·L)?

Reveal the Model Answer

The threshold error comes from many small random events, such as single dopant atoms, spread over the gate. Their number grows with the area. The spread of a sum of random events grows only as its square root. Averaged over the area, the error therefore falls as 1/√(W·L).

Self-Check
Tick each key point you covered in your answer.
Key point 1 The threshold error comes from many small random events, such as single dopant atoms, spread over the gate. Key point 2 Their number grows with the area. Key point 3 The spread of a sum of random events grows only as its square root. Key point 4 Averaged over the area, the error therefore falls as 1/√(W·L).

Misconception

"Double the width to halve the offset."

Doubling W doubles the area, which cuts σ only by √2. Halving σ needs four times the area.

Source Pelgrom, Duinmaijer and Welbers, Matching Properties of MOS Transistors, IEEE JSSC 1989
- Lesson E7.5Monte Carlo on an Amplifier's Offset
- Problem E7.5.1Offset by the Square Micrometre

What IfWhich Device to Make BiggerL2 Mid-LevelL3 Senior

Asked if they say to make every device bigger

What if you can afford more area for only one device pair? Which do you grow?

Reveal the Model Answer

Grow the pair whose share dominates the offset. Each pair's part adds as a power: the input pair one to one, the load mirror scaled by g_m3/g_m1. Four times the area of every device halves σ. Sixteen times the area of one pair leaves the other pair's part untouched, so it helps only if that pair dominated.

DC sweepPair Part and Load Part of Each Die, Pair 10/1The lab's 30 dies. Neither part dominates.

offset − mean
pair part
load part

Die 8offset − mean = -2.568 mV · pair part = -3.491 mV · load part = 869.4 µV
Die 8: the pair part is −3.49 mV and the load part +0.87 mV, together −2.62 mV. The die sits 2.57 mV below the mean: the two parts leave 0.05 mV over.
Die 17offset − mean = 5.798 mV · pair part = 2.062 mV · load part = 3.728 mV
Die 17: +2.06 mV from the pair and +3.73 mV from the load, so the die sits 5.80 mV above the mean.

Read the plot as a table

Die	offset − mean	pair part	load part
5	-1.543 mV	-1.144 mV	-434.1 µV
8	-2.568 mV	-3.491 mV	869.4 µV
10	1.395 mV	146.1 µV	1.228 mV
15	-1.191 mV	-888.5 µV	-319.6 µV
17	5.798 mV	2.062 mV	3.728 mV
20	1.413 mV	778.9 µV	682.6 µV
25	-392.1 µV	1.437 mV	-1.81 mV
30	-636.4 µV	-559 µV	-94.61 µV

Each die's offset split into the pair part and the load part. Here neither dominates, so growing one pair alone helps little.

Self-Check

Tick each key point you covered in your answer.

Key point 1 Grow the pair whose share dominates the offset. Key point 2 Each pair's part adds as a power: the input pair one to one, the load mirror scaled by g_m3/g_m1. Key point 3 Four times the area of every device halves σ. Key point 4 Sixteen times the area of one pair leaves the other pair's part untouched, so it helps only if that pair dominated.

Lesson E7.5Monte Carlo on an Amplifier's Offset

CompareProcess Corners vs Monte CarloL1 JuniorL2 Mid-Level
Compare process corners with a mismatch Monte Carlo run. Do you need both?

Reveal the Model Answer

Yes. A process corner moves every transistor of a type together, the global spread between wafers. Mismatch moves each transistor alone, the local spread on one die. Offset comes mostly from mismatch, while bias currents and speed move mostly with corners. Sign-off runs corners crossed with supply and temperature, plus Monte Carlo.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Yes. Key point 2 A process corner moves every transistor of a type together, the global spread between wafers. Key point 3 Mismatch moves each transistor alone, the local spread on one die. Key point 4 Offset comes mostly from mismatch, while bias currents and speed move mostly with corners. Key point 5 Sign-off runs corners crossed with supply and temperature, plus Monte Carlo.
Prove ItSolve E7.6.1: Nine Settings, One VerdictSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem E7.6.1
Prove ItSolve E7.5.1: Offset by the Square MicrometreSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem E7.5.1
Break ItSystematic Offset in a Two-Stage Op-AmpL2 Mid-LevelL3 Senior
What breaks the offset of a two-stage op-amp even with perfect matching, and how do you size it away?

Reveal the Model Answer

The second stage sets the first stage's output voltage. If that voltage differs from the diode node, the first stage is unbalanced, and the offset is about (V_o1 - V_x)/A_1. Size the devices so that (W/L)_6/(W/L)_4 = 2(W/L)_7/(W/L)_5. Then the first-stage output sits at V_x.

Self-Check
Tick each key point you covered in your answer.
Key point 1 The second stage sets the first stage's output voltage. Key point 2 If that voltage differs from the diode node, the first stage is unbalanced, and the offset is about (V_o1 - V_x)/A_1. Key point 3 Size the devices so that (W/L)_6/(W/L)_4 = 2(W/L)_7/(W/L)_5. Key point 4 Then the first-stage output sits at V_x.
- Lesson E5.5The Two-Stage Op-Amp

What People Get Wrong

Common wrong answers and why they fail.

Half-Truth

"Only the input pair contributes offset."

A threshold error in the load mirror refers to the input by g_m,load/g_m,pair. That was 0.57 in the lesson, so the load matters almost as much as the pair.

Source ASIC Point lesson E5.4 (measured)

Misconception

"With no mismatch in the simulation, the offset must be zero."

The topology itself puts the two halves at different drain voltages. The lesson's buffer shows -2.17 mV with perfectly matched devices.

Source ASIC Point lesson E5.4 (measured)

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