Phase Margin and the Step Response

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItCompareScale It

1. Phase Margin and the Step Response
2. WhyWhy a Buffer Is the Hardest CaseL1 JuniorL2 Mid-Level

   Why is a unity-gain buffer the hardest configuration to keep stable?

   Reveal the Model Answer

   The loop gain is the op-amp gain times the feedback factor β. In a buffer β is 1, so the loop gain is largest and crosses 1 at the highest frequency, closest to the second pole. As a gain-of-two amplifier, β is one half. The same op-amp then went from 27.3 to 37.4 degrees of margin.

   1. The input arrives

      v_in reaches the input of the amplifier. In an op-amp the difference is taken by the input pair itself: + minus −.

   2. The amplifier multiplies

      The amplifier makes v_out = A times the difference. For OTA-A, A = 136.7.

   3. A fraction comes back

      The feedback network returns β·v_out to the − input. A signal that goes once around the loop is multiplied by A and by β: the loop gain T = Aβ.

   4. The loop settles

      v_out = A(v_in − βv_out), so v_out/v_in = A/(1 + T). A buffer has β = 1 and T = A.

   Read the diagram as text

   • Input: the signal to copy
   • Difference: input minus β × output
   • Amplifier A: output = A × difference
   • Output: what the load sees
   • Feedback β: returns β × output

   • Input → Difference: input
   • Difference → Amplifier A: difference
   • Amplifier A → Output: output
   • Output → Feedback β: sample
   • Feedback β → Difference: β × output

   In the buffer of the hook, the feedback network is a wire: β = 1.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The loop gain is the op-amp gain times the feedback factor β. Key point 2 In a buffer β is 1, so the loop gain is largest and crosses 1 at the highest frequency, closest to the second pole. Key point 3 As a gain-of-two amplifier, β is one half. Key point 4 The same op-amp then went from 27.3 to 37.4 degrees of margin.

   • Lesson E6.3Phase Margin and the Step Response
   • Lesson E6.2Feedback and Loop Gain
   • Problem E6.5.1A Phase-Margin Bench for a Gain of Two
3. Prove ItSolve E6.5.1: A Phase-Margin Bench for a Gain of TwoSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem E6.5.1

4. CompareThe Miller EffectL0 FresherL1 Junior

   Compare a capacitor from an amplifier's input to ground with the same capacitor across an inverting gain stage.

   Reveal the Model Answer

   To ground, it loads the input with its own value. Across an inverting gain of -A, the far end moves A times as much the other way. So it draws (1 + A) times the current and acts like C(1 + A) at the input. In the lesson, 20 fF across the stage cut the bandwidth from 98.9 to 8.5 MHz.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 To ground, it loads the input with its own value. Key point 2 Across an inverting gain of -A, the far end moves A times as much the other way. Key point 3 So it draws (1 + A) times the current and acts like C(1 + A) at the input. Key point 4 In the lesson, 20 fF across the stage cut the bandwidth from 98.9 to 8.5 MHz.

   • Lesson E6.1Poles, Zeros and the Miller Effect
   • Problem E6.1.1Place the Pole
5. Scale ItMiller Compensation and the Right-Half-Plane ZeroL2 Mid-LevelL3 Senior

   You compensate a two-stage op-amp with C_c across the second stage, and the margin is still poor. What else is C_c doing, and how do you fix it?

   Reveal the Model Answer

   C_c splits the poles: it lowers the first pole and pushes the output pole up toward g_m6/(2πC_L). But C_c also feeds the signal forward to the output. That makes a right-half-plane zero at g_m6/(2πC_c), which lags the phase like a pole. A series R_z moves the zero. With R_z = 1/g_m6 it disappears, and a larger R_z turns it into phase lead.

   1. Two high-resistance nodes

      o1 is loaded by M2, M4 and M6's gate; out by M6, M7 and C_L. Without C_c their poles are close together.

   2. The Miller path

      C_c bridges M6, whose gain is 96.7, so o1 sees C_c(1 + A₂): 1 pF acts like 97.7 pF.

   3. M6 becomes a diode

      At high frequency C_c shorts M6's gate to its drain. The output sees about 1/g_m6 = 2.54 kΩ, and its pole moves up.

   4. The forward path

      C_c also carries current from o1 straight into out, against M6's current. Where they are equal: a zero.

      jωC_c·v_o1

   5. R_z

      A series resistor changes that current, and with it where the zero sits.

   Read the circuit as text

   • IB current source (20 µA): + → VDD, − → n1
   • MB NMOS transistor (8/1): gate → n1, drain → n1, source → 0
   • M3 PMOS transistor (8/1): gate → n2, source → VDD, drain → n2
   • M4 PMOS transistor (8/1): gate → n2, source → VDD, drain → o1
   • M1 NMOS transistor (10/1): gate → n3, drain → n2, source → n4
   • M2 NMOS transistor (10/1): gate → n5, drain → o1, source → n4
   • M5 NMOS transistor (8/1): gate → n1, drain → n4, source → 0
   • M6 PMOS transistor (32/1): gate → o1, source → VDD, drain → out
   • M7 NMOS transistor (16/1): gate → n1, drain → out, source → 0
   • R_z resistor (0 to 10 kΩ): pin 1 → o1, pin 2 → n6
   • C_c capacitor (1 pF): pin 1 → n6, pin 2 → out
   • C_L capacitor (2 pF): pin 1 → out, pin 2 → 0
   • − inn port: terminal → n3
   • + inp port: terminal → n5
   • out port: terminal → out

   OPA-B as E5.5 defines it; W/L in µm. Bodies: NMOS to ground, PMOS to VDD.

   • gain, Cc 0
   • gain, Cc 1 pF
   • phase, Cc 0
   • phase, Cc 1 pF

   1. Frequency 2.292 kHzgain, Cc 0 = 80.84 dB · gain, Cc 1 pF = 77.84 dB · phase, Cc 0 = -0.6459° · phase, Cc 1 pF = -44.94°

      With 1 pF the gain is 3 dB down at 2.292 kHz. Without C_c the first pole sits at 225.3 kHz, 98 times higher.

   2. Frequency 20.79 MHzgain, Cc 0 = 20.4 dB · gain, Cc 1 pF = -0.003816 dB · phase, Cc 0 = -179.8° · phase, Cc 1 pF = -152.7°

      With 1 pF the gain crosses 0 dB at 20.79 MHz, where the phase is −152.7°.

   3. Frequency 66.19 MHzgain, Cc 0 = -0.004216 dB · gain, Cc 1 pF = -13.97 dB · phase, Cc 0 = -194.9° · phase, Cc 1 pF = -219.8°

      Without C_c the gain crosses 0 dB at 66.19 MHz, where the phase is −194.9°. That is past −180°, so a buffer made from it oscillates.

   Read the plot as a table

   Frequency	gain, Cc 0	gain, Cc 1 pF	phase, Cc 0	phase, Cc 1 pF
   10 Hz	80.84 dB	80.84 dB	-0.002817°	-0.2495°
   100 Hz	80.84 dB	80.83 dB	-0.02818°	-2.493°
   1 kHz	80.84 dB	80.09 dB	-0.2818°	-23.53°
   2.292 kHz	80.84 dB	77.84 dB	-0.6459°	-44.94°
   10 kHz	80.83 dB	67.84 dB	-2.816°	-77.1°
   100 kHz	80.07 dB	48.06 dB	-26.75°	-89.03°
   1 MHz	66.67 dB	28.06 dB	-106.3°	-93.28°
   10 MHz	33.03 dB	7.568 dB	-171.1°	-123°
   20.79 MHz	20.4 dB	-0.003816 dB	-179.8°	-152.7°
   66.19 MHz	-0.004216 dB	-13.97 dB	-194.9°	-219.8°
   100 MHz	-7.551 dB	-18.86 dB	-202.8°	-243°
   1 GHz	-46.93 dB	-42.45 dB	-270.3°	-309.8°

   Pole splitting, measured. With C_c = 1 pF the first pole drops 98 times and the buffer no longer passes -180° at f_u.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 C_c splits the poles: it lowers the first pole and pushes the output pole up toward g_m6/(2πC_L). Key point 2 But C_c also feeds the signal forward to the output. Key point 3 That makes a right-half-plane zero at g_m6/(2πC_c), which lags the phase like a pole. Key point 4 A series R_z moves the zero. Key point 5 With R_z = 1/g_m6 it disappears, and a larger R_z turns it into phase lead.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer explains pole splitting and names the right-half-plane zero. It fixes the zero with a nulling resistor.

   Misconception

   "A bigger C_c always buys more margin."

   It lowers f_u but leaves the right-half-plane zero lagging the phase. On this op-amp, 1 pF with no R_z gives 27.3 degrees. With R_z = 5 kΩ the same C_c gives 60.1 degrees.

   Run It

   OPA-B open loop from lesson E6.4: C_c = 1 pF with R_z shorted (1 mΩ), 2 pF load.

   SPICEngspice 42 · simulator service

   Edit the netlist, then run it

   OutputPlots

   RunReset codeExpected: pm = 2.731987e+01 fz_hand = 6.260970e+07

   See the Fix

   * E6.4 lab: OPA-B open loop on the inductor bench; C_c, R_z and C_L are parameters
   .lib sky130 tt
   .param cc=1p rz=5k cl=2p
   VDD vdd 0 1.8
   IB vdd nb 20u
   XMB nb nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
   * stage one: M1 (diode side) takes the - input, M2 the + input
   XM5 tail nb 0 0 sky130_fd_pr__nfet_01v8 W=8 L=1
   XM1 x inn tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
   XM2 o1 inp tail 0 sky130_fd_pr__nfet_01v8 W=10 L=1
   XM3 x x vdd vdd sky130_fd_pr__pfet_01v8 W=8 L=1
   XM4 o1 x vdd vdd sky130_fd_pr__pfet_01v8 W=8 L=1
   * stage two
   XM6 out o1 vdd vdd sky130_fd_pr__pfet_01v8 W=32 L=1
   XM7 out nb 0 0 sky130_fd_pr__nfet_01v8 W=16 L=1
   * the compensation under test
   RZ o1 z {rz}
   CC z out {cc}
   CL out 0 {cl}
   * AC on the + input; 1 TH and 1 F close the loop for DC only, so v(out) is the loop gain T
   VIN inp 0 DC 0.9 AC 1
   LF out inn 1T
   CF inn 0 1
   .control
   op
   let gm1 = @m.xm1.msky130_fd_pr__nfet_01v8[gm]
   let gm6 = @m.xm6.msky130_fd_pr__pfet_01v8[gm]
   let ccv = @cc[capacitance]
   let rzv = @rz[resistance]
   let clv = @cl[capacitance]
   ac dec 50 1 10g
   let one = 1+0*vdb(out)
   let pmv = 180+180/pi*cph(v(out))
   meas ac a0 FIND vdb(out) AT=10
   meas ac fu WHEN vdb(out)=0
   meas ac pm FIND pmv AT=fu
   * hand numbers: 1/gm6, p2 = gm6/(2 pi CL), and (for C_c above 0) f_u and the zero
   let rzn = 1/op1.gm6*one
   let p2h = op1.gm6/(2*pi*op1.clv)*one
   meas ac rz_null FIND rzn AT=10
   meas ac p2_hand FIND p2h AT=10
   if op1.ccv gt 0
   let fuh = op1.gm1/(2*pi*op1.ccv)*one
   let fzh = 1/(2*pi*op1.ccv*(1/op1.gm6-op1.rzv))*one
   meas ac fu_hand FIND fuh AT=10
   meas ac fz_hand FIND fzh AT=10
   end
   .endc
   .end
   

   Prints: pm = 6.008520e+01 rz_null = 2.542018e+03 fz_hand = -6.475026e+07

   Half-Truth

   "Set R_z as large as possible to get the most phase lead."

   Too large an R_z pushes f_u up into the higher poles and the margin falls again. Place the zero near the worst-case output pole, then measure.

   Source ASIC Point lesson E6.4

   • Lesson E6.4Miller Compensation and the Right-Half-Plane Zero
   • Lesson E6.6Capstone: Compensate a Two-Stage Op-Amp
   • Problem E6.4.1The Buffer That a Bigger C_c Slowed
   • Problem E6.6.1Stable from 1 to 5 pF on Less Current
6. WhyWhy the Feed-Forward Zero HurtsL2 Mid-Level

   Why does a right-half-plane zero hurt stability when an ordinary zero helps?

   Reveal the Model Answer

   A left-half-plane zero adds phase lead as the gain rises. A right-half-plane zero raises the gain in the same way but adds phase lag instead. So it costs margin like a pole while it slows the gain's fall. In a Miller op-amp it comes from current that C_c passes forward from the first stage to the output.

   • gain, Cc 1 pF
   • gain, Cc 0
   • phase, Cc 1 pF
   • phase, Cc 0

   1. Frequency 1 kHzgain, Cc 1 pF = 39.71 dB · gain, Cc 0 = 39.71 dB · phase, Cc 1 pF = 179.7° · phase, Cc 0 = 179.8°

      At 1 kHz the stage gives 39.71 dB and the phase is 179.7°: it inverts.

   2. Frequency 1 MHzgain, Cc 1 pF = 26.11 dB · gain, Cc 0 = 29.37 dB · phase, Cc 1 pF = 101.1° · phase, Cc 0 = 107.7°

      Past the output pole the phase is 101.1° with C_c and 107.7° without. One pole has taken close to 90°.

   3. Frequency 59.54 MHzgain, Cc 1 pF = -6.147 dB · gain, Cc 0 = -5.69 dB · phase, Cc 1 pF = 45° · phase, Cc 0 = 87.24°

      With 1 pF the phase reaches 45° at 59.54 MHz (hand: 62.6 MHz). Without C_c it is still 87.2°.

   4. Frequency 1 GHzgain, Cc 1 pF = -9.083 dB · gain, Cc 0 = -27.54 dB · phase, Cc 1 pF = 3.419° · phase, Cc 0 = 47.49°

      With 1 pF the gain has flattened at −9.08 dB and the phase is 3.4°: out follows o1 through C_c. Without C_c: −27.54 dB and falling.

   Read the plot as a table

   Frequency	gain, Cc 1 pF	gain, Cc 0	phase, Cc 1 pF	phase, Cc 0
   1 kHz	39.71 dB	39.71 dB	179.7°	179.8°
   10 kHz	39.7 dB	39.7 dB	177.3°	178.2°
   100 kHz	38.85 dB	39.3 dB	154.8°	162.6°
   1 MHz	26.11 dB	29.37 dB	101.1°	107.7°
   10 MHz	6.421 dB	9.787 dB	81.62°	91.31°
   59.54 MHz	-6.147 dB	-5.69 dB	45°	87.24°
   100 MHz	-7.82 dB	-10.17 dB	30.74°	85.04°
   1 GHz	-9.083 dB	-27.54 dB	3.419°	47.49°

   The second stage driven alone. With C_c the gain flattens at high frequency while the phase still lags: the zero in the right half-plane.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A left-half-plane zero adds phase lead as the gain rises. Key point 2 A right-half-plane zero raises the gain in the same way but adds phase lag instead. Key point 3 So it costs margin like a pole while it slows the gain's fall. Key point 4 In a Miller op-amp it comes from current that C_c passes forward from the first stage to the output.

   • Lesson E6.1Poles, Zeros and the Miller Effect
   • Lesson E6.4Miller Compensation and the Right-Half-Plane Zero
7. WhyWhere the Right-Half-Plane Zero SitsL2 Mid-LevelL3 Senior

   Why does the zero sit at g_m6/(2πC_c), and why does a bigger C_c not fix it?

   Reveal the Model Answer

   At the zero, the current that C_c feeds forward equals the current the second stage sinks, so they cancel at the output. The forward current grows with frequency as s·C_c, and the stage current is set by g_m6. They meet at g_m6/(2πC_c). A bigger C_c lowers this zero, and it lowers f_u by the same factor.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 At the zero, the current that C_c feeds forward equals the current the second stage sinks, so they cancel at the output. Key point 2 The forward current grows with frequency as s·C_c, and the stage current is set by g_m6. Key point 3 They meet at g_m6/(2πC_c). Key point 4 A bigger C_c lowers this zero, and it lowers f_u by the same factor.

   Misconception

   "Make C_c bigger to push the zero away."

   A bigger C_c lowers the zero frequency. It also lowers f_u = g_m1/(2πC_c), so the ratio between them stays g_m6/g_m1.

   Source Lesson E6.4 key points

   • Lesson E6.4Miller Compensation and the Right-Half-Plane Zero
   • Problem E6.4.1The Buffer That a Bigger C_c Slowed
8. What IfNulling the Zero with R_z = 1/g_m6L2 Mid-LevelL3 Senior

   Asked if they set R_z to exactly 1/g_m6

   What if you set R_z exactly to 1/g_m6, about 2.54 kΩ here, as in the parameter line below?

   .param cc=1p rz=2542 cl=2p
   RZ o1 z {rz}
   CC z out {cc}
   CL out 0 {cl}

   Reveal the Model Answer

   The zero moves out to a very high frequency, so it no longer lags the phase. On this op-amp the margin rises from 27.3 to 45.1 degrees. That is better but still short of 60, because the output pole is still close to f_u. A slightly larger R_z, here 5 kΩ, puts a helpful zero near that pole.

   • Rz 0
   • Rz 2.54 kΩ
   • Rz 5 kΩ
   • Rz 10 kΩ

   1. Frequency 20.33 MHzRz 0 = -151.6° · Rz 2.54 kΩ = -134.9° · Rz 5 kΩ = -118.8° · Rz 10 kΩ = -95.21°

      With R_z = 2.54 kΩ the zero is gone: 45.1° of margin at 20.33 MHz.

   2. Frequency 21.43 MHzRz 0 = -154.2° · Rz 2.54 kΩ = -136.8° · Rz 5 kΩ = -119.9° · Rz 10 kΩ = -96.05°

      With 5 kΩ a left-half-plane zero near 65 MHz lifts the margin to 60.1°.

   3. Frequency 31.89 MHzRz 0 = -176.1° · Rz 2.54 kΩ = -152.2° · Rz 5 kΩ = -129.2° · Rz 10 kΩ = -105.5°

      With 10 kΩ the zero near 21 MHz lifts the gain too, so f_u moves up to 31.89 MHz, with 74.5° of margin.

   Read the plot as a table

   Frequency	Rz 0	Rz 2.54 kΩ	Rz 5 kΩ	Rz 10 kΩ
   100 kHz	-89.03°	-88.94°	-88.85°	-88.67°
   1 MHz	-93.28°	-92.38°	-91.5°	-89.72°
   10 MHz	-123°	-114.2°	-105.7°	-89.89°
   20.33 MHz	-151.6°	-134.9°	-118.8°	-95.21°
   21.43 MHz	-154.2°	-136.8°	-119.9°	-96.05°
   31.89 MHz	-176.1°	-152.2°	-129.2°	-105.5°
   100 MHz	-243°	-201.6°	-161.6°	-160.1°
   1 GHz	-309.8°	-293.5°	-278.3°	-273.1°

   Measured on ngspice 42; the table lists all nine copies of the run.

   SPICEngspice 42 · simulator service

   Edit the netlist, then run it

   OutputPlots

   RunReset codeExpected: pm = 4.512441e+01 rz_null = 2.542018e+03

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The zero moves out to a very high frequency, so it no longer lags the phase. Key point 2 On this op-amp the margin rises from 27.3 to 45.1 degrees. Key point 3 That is better but still short of 60, because the output pole is still close to f_u. Key point 4 A slightly larger R_z, here 5 kΩ, puts a helpful zero near that pole.

   • Lesson E6.4Miller Compensation and the Right-Half-Plane Zero
9. CompareMore Current vs a Placed ZeroL3 Senior

   Compare two ways to meet a 10 MHz target at a 5 pF load: more second-stage current, or a zero placed with R_z.

   Reveal the Model Answer

   With the zero cancelled, f_u must stay below the output pole divided by 2.2. In the lesson that capped the op-amp at 5.77 MHz, and 10 MHz needed 2.5 times the second-stage current. Placing a left-half-plane zero near the worst output pole met the brief at the original current, with 1.75 pF and 8 kΩ. The price is sensitivity to R_z and to the load.

   1. Find the worst case

      The output pole falls with C_L, so 5 pF decides the design.

   2. The textbook route

      With the zero cancelled, 60° at 5 pF allows only 5.77 MHz. Doubling the bandwidth needs about 2.5 times the second-stage current.

   3. Use the zero

      A left-half-plane zero near p₂ recovers the phase at the original current. Then verify every load, the step, and R_z 20 % off.

   Read the diagram as text

   • Brief: 60°, 10 MHz, 1 to 5 pF
   • Worst load: 5 pF: p2 near 12.5 MHz
   • Cancel the zero: Rz = 1/gm6: 5.77 MHz
   • More current: 2.5x stage two: 254 uW
   • Use the zero: Rz = 8 k, Cc = 1.75 pF
   • Verify: every load, a step, Rz +-20 %

   • Brief → Worst load: find
   • Worst load → Cancel the zero: try
   • Cancel the zero → More current: too slow
   • Cancel the zero → Use the zero: or
   • Use the zero → Verify: measure
   • More current → Use the zero: compare

   Every number is from the comparison run in the next figure.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 With the zero cancelled, f_u must stay below the output pole divided by 2.2. Key point 2 In the lesson that capped the op-amp at 5.77 MHz, and 10 MHz needed 2.5 times the second-stage current. Key point 3 Placing a left-half-plane zero near the worst output pole met the brief at the original current, with 1.75 pF and 8 kΩ. Key point 4 The price is sensitivity to R_z and to the load.

   • Lesson E6.6Capstone: Compensate a Two-Stage Op-Amp
   • Problem E6.6.1Stable from 1 to 5 pF on Less Current
10. Prove ItSolve E6.6.1: Stable from 1 to 5 pF on Less CurrentSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem E6.6.1

11. Prove ItSolve E6.4.1: The Buffer That a Bigger C_c SlowedSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem E6.4.1