Skew, Latency and Insertion Delay

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompareScale It

1. Skew, Latency and Insertion Delay
2. WhyWhy Only Local Skew Enters a SlackL1 Junior

   Why does skew between two flops with no path between them not matter for timing?

   Reveal the Model Answer

   A setup or hold check compares one launch flop with one capture flop along a path. If no path joins two flops, no check ever compares their clocks, so their latency difference never appears in any slack. It can still matter for power and for clock-domain interfaces, but not for these checks.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A setup or hold check compares one launch flop with one capture flop along a path. Key point 2 If no path joins two flops, no check ever compares their clocks, so their latency difference never appears in any slack. Key point 3 It can still matter for power and for clock-domain interfaces, but not for these checks.

   • Lesson L5.1Skew, Latency and Insertion Delay
3. Prove ItSolve L5.1.1: Separate Local Skew from Clock SpreadSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L5.1.1

4. CompareA Strong Clock Tree vs a Weak OneL1 JuniorL2 Mid-Level

   Compare a clock tree built from large buffers with one built from small buffers.

   Reveal the Model Answer

   Large buffers give sharp edges, low insertion delay and low skew. They cost area and clock power, since the clock switches every cycle. In lesson L5.2 the default tree on the MAC had 0.31 ns insertion delay and 0.008 ns skew at 0.257 mW. A clkbuf_1 tree had about 0.73 ns, 0.045 ns and 0.166 mW. Clocks route on upper, low-resistance metal for the same reason.

   1. Split the region

      The topology cuts the area of the sinks in two, then each half in two again. Each cut is a level of the H-tree.

   2. One buffer per quadrant

      A leaf buffer sits in each quarter and drives the flops there: 12, 13, 14, 13. The wires from the root to each leaf are about the same length.

   3. Even out the loads

      CTS added 3 dummy loads: clock cells that drive nothing. They make the lightly loaded leaves as slow as the heavy ones.

   Read the diagram as text

   • clk port: drives the root only
   • clkbuf_0_clk: clkbuf_8, centre
   • clkbuf_2_3__f_clk: 12 flops + 1 dummy
   • clkbuf_2_2__f_clk: 13 flops + 1 dummy
   • clkbuf_2_1__f_clk: 14 flops
   • clkbuf_2_0__f_clk: 13 flops + 1 dummy

   • clk port → clkbuf_0_clk: clk
   • clkbuf_0_clk → clkbuf_2_3__f_clk: clock
   • clkbuf_0_clk → clkbuf_2_2__f_clk: clock
   • clkbuf_0_clk → clkbuf_2_1__f_clk: clock
   • clkbuf_0_clk → clkbuf_2_0__f_clk: clock

   The default tree on lesson L5.2's MAC: a two-level H-tree. Names are the ones CTS writes.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Large buffers give sharp edges, low insertion delay and low skew. Key point 2 They cost area and clock power, since the clock switches every cycle. Key point 3 In lesson L5.2 the default tree on the MAC had 0.31 ns insertion delay and 0.008 ns skew at 0.257 mW. Key point 4 A clkbuf_1 tree had about 0.73 ns, 0.045 ns and 0.166 mW. Key point 5 Clocks route on upper, low-resistance metal for the same reason.

   • Lesson L5.2Building the Tree
   • Problem L5.2.1Check the Clock-Tree Handoff
5. What IfWhat a Slow Clock Edge Does to a FlopL1 JuniorL2 Mid-Level

   What if the clock edge reaching a flop is very slow?

   Reveal the Model Answer

   The flop gets slower and its timing window moves. In the sky130 library, clock-to-Q of dfxtp_1 grows from about 0.27 to 0.52 ns as the clock slew goes from 0.01 to 1.5 ns. The setup and hold times shift too. That is why clock trees keep edges sharp and why a clock slew limit is part of CTS.

   • clock to Q (falling Q)
   • Q slew (falling)

   1. Clock slew 100 psclock to Q (falling Q) = 305.5 ps · Q slew (falling) = 22.6 ps

      At a 0.1 ns clock slew: clock-to-Q 0.3055 ns, Q slew 0.0226 ns.

   2. Clock slew 1.5 nsclock to Q (falling Q) = 510.5 ps · Q slew (falling) = 22.6 ps

      At 1.5 ns the clock-to-Q is 0.5105 ns, but the Q slew is still 0.0226 ns.

   Read the plot as a table

   Clock slew	clock to Q (falling Q)	Q slew (falling)
   100 ps	305.5 ps	22.6 ps
   200 ps	336.7 ps	22.6 ps
   400 ps	382.4 ps	22.65 ps
   600 ps	415.3 ps	22.7 ps
   800 ps	442.4 ps	22.68 ps
   1 ns	461.9 ps	22.6 ps
   1.2 ns	481.3 ps	22.6 ps
   1.4 ns	500.8 ps	22.6 ps
   1.5 ns	510.5 ps	22.6 ps

   Measured on dfxtp_1, falling Q. Clock-to-Q grows as the clock edge slows, while the Q edge itself stays sharp.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The flop gets slower and its timing window moves. Key point 2 In the sky130 library, clock-to-Q of dfxtp_1 grows from about 0.27 to 0.52 ns as the clock slew goes from 0.01 to 1.5 ns. Key point 3 The setup and hold times shift too. Key point 4 That is why clock trees keep edges sharp and why a clock slew limit is part of CTS.

   • Lesson L5.1Skew, Latency and Insertion Delay
6. Scale ItUseful Skew: Borrowing Time Between StagesL2 Mid-LevelL3 Senior

   Asked if they say all skew is bad

   Stage A into register R fails setup by 0.34 ns, and the stage after R has 0.70 ns to spare. A colleague adds the latency below on R's clock. Does it work, and how far can you push it?

   create_clock -name clk -period 1.25 [get_ports clk]
   set_clock_transition 0.1 [all_clocks]
   set_clock_latency 0.4 [get_pins {r0/CLK r1/CLK}]
   group_path -name stageA -to [get_pins r1/D]
   group_path -name intoR -to [get_pins r0/D]
   group_path -name stageB -to [get_pins b/D]

   Reveal the Model Answer

   Yes: delaying R's clock by 0.4 ns gives stage A 0.4 ns more and takes 0.4 ns from the stage after R, so both pass. The limit is hold into R, which loses the same 0.4 ns; at 0.6 ns stage A gains more but hold into R fails. Around any loop of registers the skews sum to zero. The delay must later be built from real clock cells, in steps.

   • stage A setup
   • stage B setup
   • hold into R

   1. Latency of R 0 sstage A setup = -341.5 ps · stage B setup = 696.4 ps · hold into R = 474.2 ps

      No skew: stage A -0.3415 ns, stage B 0.6964 ns, hold into R 0.4742 ns.

   2. Latency of R 400 psstage A setup = 58.5 ps · stage B setup = 296.4 ps · hold into R = 74.2 ps

      0.4 ns: stage A 0.0585 ns, stage B 0.2964 ns, hold 0.0742 ns. Every check passes.

   3. Latency of R 500 psstage A setup = 158.5 ps · stage B setup = 196.4 ps · hold into R = -25.8 ps

      0.5 ns: hold into R is -0.0258 ns. The late edge now catches the next value on the short path.

   Read the plot as a table

   Latency of R	stage A setup	stage B setup	hold into R
   0 s	-341.5 ps	696.4 ps	474.2 ps
   100 ps	-241.5 ps	596.4 ps	374.2 ps
   200 ps	-141.5 ps	496.4 ps	274.2 ps
   300 ps	-41.5 ps	396.4 ps	174.2 ps
   400 ps	58.5 ps	296.4 ps	74.2 ps
   400 ps	58.5 ps	296.4 ps	74.2 ps
   500 ps	158.5 ps	196.4 ps	-25.8 ps
   600 ps	258.5 ps	96.4 ps	-125.8 ps

   The three checks of this question against the latency on R. At 0.4 ns all pass. Past it, hold into R fails first.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Yes: delaying R's clock by 0.4 ns gives stage A 0.4 ns more and takes 0.4 ns from the stage after R, so both pass. Key point 2 The limit is hold into R, which loses the same 0.4 ns; at 0.6 ns stage A gains more but hold into R fails. Key point 3 Around any loop of registers the skews sum to zero. Key point 4 The delay must later be built from real clock cells, in steps.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer shows that a later capture clock gives setup time to the stage before. It takes the same time from the stage after. It then checks hold into the delayed register.

   Missed Corner

   "More latency on R just makes stage A faster; push it until setup is comfortable."

   Hold into R loses whatever stage A gains. At 0.6 ns stage A has 0.26 ns spare but hold into R fails by 0.13 ns; at 0.4 ns every check passes.

   Run It

   The pipeline from lesson L5.4 with 0.6 ns of latency on R's clock pins.

   create_clock -name clk -period 1.25 [get_ports clk]
   set_clock_transition 0.1 [all_clocks]
   set_clock_latency 0.6 [get_pins {r0/CLK r1/CLK}]
   group_path -name stageA -to [get_pins r1/D]
   group_path -name intoR -to [get_pins r0/D]
   group_path -name stageB -to [get_pins b/D]
   

   Prints: 1.1579 slack (MET) 0.2585 slack (MET) 0.0964 slack (MET) -0.1258 slack (VIOLATED)

   See the Fix

   create_clock -name clk -period 1.25 [get_ports clk]
   set_clock_transition 0.1 [all_clocks]
   set_clock_latency 0.4 [get_pins {r0/CLK r1/CLK}]
   group_path -name stageA -to [get_pins r1/D]
   group_path -name intoR -to [get_pins r0/D]
   group_path -name stageB -to [get_pins b/D]
   

   Prints: 0.9579 slack (MET) 0.0585 slack (MET) 0.2964 slack (MET) 0.0742 slack (MET)

   Misconception

   "Useful skew can fix a slow self-loop too."

   A register feeding itself sees the same latency at launch and capture, so the skew is zero by construction. Around any register cycle the skews sum to zero.

   Source ASIC Point lesson L5.4 (MAC acc -> acc slack unchanged at -0.0959 ns, measured)

   • Lesson L5.4Useful Skew: Borrowing Time Between Stages
   • Problem L5.4.1Schedule Three Capture Clocks
7. WhyWhy Skew Around a Loop Sums to ZeroL2 Mid-LevelL3 Senior

   Why can useful skew not speed up a loop of registers as a whole?

   Reveal the Model Answer

   Each register's latency is added to the stage it captures and subtracted from the stage it launches. Walk around a loop and every latency appears once with each sign, so the total time available to the loop is unchanged. The best you can do is share it evenly, so the period is bounded by the loop's average stage delay.

   1. A path that skew can help

      p → adder → acc: delaying acc gives it time, taken from paths that start at acc.

   2. A common vector latency cancels

      acc is a vector. This path crosses different bits; giving every bit the same latency moves both ends equally.

   Read the diagram as text

   • ra, rb: operand registers
   • multiplier: stage into p
   • p: product register
   • adder: acc + p
   • acc: accumulator

   • ra, rb → multiplier: data
   • multiplier → p: data
   • p → adder: data
   • adder → acc: sum
   • acc → adder: acc

   The MAC has one loop: acc feeds the adder that feeds acc. Skew on acc helps one side of the loop and hurts the other.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Each register's latency is added to the stage it captures and subtracted from the stage it launches. Key point 2 Walk around a loop and every latency appears once with each sign, so the total time available to the loop is unchanged. Key point 3 The best you can do is share it evenly, so the period is bounded by the loop's average stage delay.

   • Lesson L5.4Useful Skew: Borrowing Time Between Stages
8. CompareUseful Skew vs RetimingL2 Mid-LevelL3 Senior

   Compare useful skew with retiming, which moves logic across the register instead.

   Reveal the Model Answer

   Useful skew moves the clock edge and leaves the logic alone. So it costs clock cells and hold margin, and it is invisible to the RTL. Retiming moves gates across the register, which changes the state encoding and needs equivalence checking and sometimes reset changes. Skew is the late, physical fix. Retiming or pipelining is the structural fix when a stage is too long for any clock trick.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Useful skew moves the clock edge and leaves the logic alone. Key point 2 So it costs clock cells and hold margin, and it is invisible to the RTL. Key point 3 Retiming moves gates across the register, which changes the state encoding and needs equivalence checking and sometimes reset changes. Key point 4 Skew is the late, physical fix. Key point 5 Retiming or pipelining is the structural fix when a stage is too long for any clock trick.

   • Lesson L5.4Useful Skew: Borrowing Time Between Stages
   • Lesson L4.5Timing-Driven Placement and the First Wire Delays
9. Break ItBuilding Skew from Real Clock CellsL2 Mid-LevelL3 Senior

   The SDC latency of 0.4 ns must now be built from clock delay cells. The measured options are below. Which do you pick?

   R latency built with (propagated clock, lesson L5.4, measured)
   2 x clkdlybuf4s18_1   latency 0.3935 ns   stage A +0.0399   hold into R +0.0875
   1 x clkdlybuf4s50_1   latency 0.4927 ns   hold into R -0.0129
   1 x clkdlybuf4s25_1   latency 0.2688 ns   stage A -0.0833

   Reveal the Model Answer

   Two clkdlybuf4s18_1 cells, the only option that passes both checks. Real cells come in steps, so the built latency rarely matches the SDC number. The window between hold into R and setup of stage A decides which steps are usable. The branch to R is also not shared with the other flops, so its variation is not cancelled by reconvergence pessimism removal.

   a1 → r1setup check, latest arrival7 cells

   • Clock latency
   • Cell delay
   • Setup time

   1. Launch

      a0 is clocked straight from the port, so its launch latency is 0.0000 ns.

   2. Built latency

      R's clock arrives 0.3935 ns late, through the two delay buffers.

   3. Met

      Stage A meets setup with the built delay, at a slack of 0.0399 ns.

   Read the path as a table

   Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns. Capture: clk rise edge at 1.2500 ns, latency 0.3935 ns, library setup time −0.1217 ns.

   Arrival 1.4819 ns, required 1.5218 ns, slack 0.0399 ns (met).

   Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
   1	a1/CLK → a1/Q	dfxtp_1	rise	0.4872	0.4872	0.2741
   	a1/Q → m1/B	wire qa1	rise	0.0000	0.4872	0.2741
   2	m1/B → m1/X	xor2_1	fall	0.1173	0.6045	0.0897
   	m1/X → m2/A	wire s1	fall	0.0000	0.6045	0.0897
   3	m2/A → m2/X	xor2_1	fall	0.1781	0.7827	0.0897
   	m2/X → m3/A	wire s2	fall	0.0000	0.7827	0.0897
   4	m3/A → m3/X	xor2_1	fall	0.1781	0.9608	0.0897
   	m3/X → m4/A	wire s3	fall	0.0000	0.9608	0.0897
   5	m4/A → m4/X	xor2_1	fall	0.1781	1.1389	0.0897
   	m4/X → m5/A	wire s4	fall	0.0000	1.1389	0.0897
   6	m5/A → m5/X	xor2_1	fall	0.1781	1.3170	0.0897
   	m5/X → m6/A	wire s5	fall	0.0000	1.3170	0.0897
   7	m6/A → m6/X	xor2_1	fall	0.1649	1.4819	0.0723
   	m6/X → r1/D	wire s6	fall	0.0000	1.4819	0.0723

   The report

   Startpoint: a1 (rising edge-triggered flip-flop clocked by clk)
   Endpoint: r1 (rising edge-triggered flip-flop clocked by clk)
   Path Group: stageA
   Path Type: max
   
   Fanout       Cap      Slew     Delay      Time   Description
   -------------------------------------------------------------------------------------
                                 0.0000    0.0000   clock clk (rise edge)
                                 0.0000    0.0000   clock source latency
        4    0.0079    0.1000    0.0000    0.0000 ^ clk (in)
                                                    clk (net)
                       0.1000    0.0000    0.0000 ^ a1/CLK (sky130_fd_sc_hd__dfxtp_1)
        7    0.0286    0.2741    0.4872    0.4872 ^ a1/Q (sky130_fd_sc_hd__dfxtp_1)
                                                    qa1 (net)
                       0.2741    0.0000    0.4872 ^ m1/B (sky130_fd_sc_hd__xor2_1)
        1    0.0042    0.0897    0.1173    0.6045 v m1/X (sky130_fd_sc_hd__xor2_1)
                                                    s1 (net)
                       0.0897    0.0000    0.6045 v m2/A (sky130_fd_sc_hd__xor2_1)
        1    0.0042    0.0897    0.1781    0.7827 v m2/X (sky130_fd_sc_hd__xor2_1)
                                                    s2 (net)
                       0.0897    0.0000    0.7827 v m3/A (sky130_fd_sc_hd__xor2_1)
        1    0.0042    0.0897    0.1781    0.9608 v m3/X (sky130_fd_sc_hd__xor2_1)
                                                    s3 (net)
                       0.0897    0.0000    0.9608 v m4/A (sky130_fd_sc_hd__xor2_1)
        1    0.0042    0.0897    0.1781    1.1389 v m4/X (sky130_fd_sc_hd__xor2_1)
                                                    s4 (net)
                       0.0897    0.0000    1.1389 v m5/A (sky130_fd_sc_hd__xor2_1)
        1    0.0042    0.0897    0.1781    1.3170 v m5/X (sky130_fd_sc_hd__xor2_1)
                                                    s5 (net)
                       0.0897    0.0000    1.3170 v m6/A (sky130_fd_sc_hd__xor2_1)
        1    0.0017    0.0723    0.1649    1.4819 v m6/X (sky130_fd_sc_hd__xor2_1)
                                                    s6 (net)
                       0.0723    0.0000    1.4819 v r1/D (sky130_fd_sc_hd__dfxtp_1)
                                           1.4819   data arrival time
   
                                 1.2500    1.2500   clock clk (rise edge)
                                 0.0000    1.2500   clock source latency
        4    0.0079    0.1000    0.0000    1.2500 ^ clk (in)
                                                    clk (net)
                       0.1000    0.0000    1.2500 ^ dl1/A (sky130_fd_sc_hd__clkdlybuf4s18_1)
        1    0.0023    0.0352    0.2029    1.4529 ^ dl1/X (sky130_fd_sc_hd__clkdlybuf4s18_1)
                                                    rc1 (net)
                       0.0352    0.0000    1.4529 ^ dl2/A (sky130_fd_sc_hd__clkdlybuf4s18_1)
        2    0.0038    0.0482    0.1906    1.6435 ^ dl2/X (sky130_fd_sc_hd__clkdlybuf4s18_1)
                                                    rc2 (net)
                       0.0482    0.0000    1.6435 ^ r1/CLK (sky130_fd_sc_hd__dfxtp_1)
                                 0.0000    1.6435   clock reconvergence pessimism
                                -0.1217    1.5218   library setup time
                                           1.5218   data required time
   -------------------------------------------------------------------------------------
                                           1.5218   data required time
                                          -1.4819   data arrival time
   -------------------------------------------------------------------------------------
                                           0.0399   slack (MET)

   Stage A with R's clock through two real delay buffers: setup passes with 0.0399 ns to spare.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Two clkdlybuf4s18_1 cells, the only option that passes both checks. Key point 2 Real cells come in steps, so the built latency rarely matches the SDC number. Key point 3 The window between hold into R and setup of stage A decides which steps are usable. Key point 4 The branch to R is also not shared with the other flops, so its variation is not cancelled by reconvergence pessimism removal.

   • Lesson L5.4Useful Skew: Borrowing Time Between Stages
   • Lesson L2.9Corners, Derates, OCV and CPPR
   • Problem L5.4.1Schedule Three Capture Clocks
10. Prove ItSolve L5.4.1: Schedule Three Capture ClocksSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem L5.4.1

11. WhyWhy CPPR Does Not Cover the Delay BranchL2 Mid-LevelL3 Senior

    Why is the variation on the branch to R not cancelled by reconvergence pessimism removal?

    Reveal the Model Answer

    CPPR credits only the clock segment that launch and capture share, because one wire cannot be early and late at once. The delay cells sit on the branch to R alone. So the tool still derates them late for one side and early for the other. That variation shrinks the usable window.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 CPPR credits only the clock segment that launch and capture share, because one wire cannot be early and late at once. Key point 2 The delay cells sit on the branch to R alone. Key point 3 So the tool still derates them late for one side and early for the other. Key point 4 That variation shrinks the usable window.

    Misconception

    "CPPR removes all clock variation from the report."

    It removes only the shared part. Every cell after the branch point still carries its full derate.

    Source Lesson L2.9 key points

    • Lesson L5.4Useful Skew: Borrowing Time Between Stages
    • Lesson L2.9Corners, Derates, OCV and CPPR