Interview Question · Debug
A Power Grid That Will Not Build
- Likely at Infineon
The Question
The interviewer asks
Your floorplan stops in power-grid generation with the error shown in the answer. What does it mean, and what are your options?
You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
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You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
The core is 28.52 µm wide. But one pair of met4 straps needs a 13.6 µm offset plus 15.2 µm of strap width, about 28.7 µm. So the grid cannot fit even once. Widen the core by lowering utilization or changing the aspect ratio. Or use a grid definition with narrower straps or a smaller offset for small blocks. The grid is part of the floorplan, not something added after it.
Read the diagram as text
- met5 strap: The block's VDD pins
- via4: met5 to met4
- met4 strap: Vertical, 1.6 µm wide
- Via stack: via3, via2, via
- met1 rail: 0.48 µm wide
- Cell: VPWR pin
- met5 strap → via4
- via4 → met4 strap
- met4 strap → Via stack
- Via stack → met1 rail
- met1 rail → Cell
The grid in this error, from the top: met5 and met4 straps, via stacks, then the met1 rail of each row.
[ERROR PDN-0185] Insufficient width (28.52 um) to add straps on layer met4 in grid "grid" with total strap width 15.2 um and offset 13.6 um.Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Junior)
A good junior answer reads the numbers in the error message. It sees that the core is narrower than one pair of straps, and suggests a wider core.
What Interviewers Listen For (Mid-Level)
A good mid-level answer explains how the sky130 grid is built. It weighs strap pitch against routing tracks and IR drop. It checks the global power connections before it blames the grid.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyProve ItBreak ItCompare
- A Power Grid That Will Not Build
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WhyHow the sky130 Power Grid Is BuiltL1 JuniorL2 Mid-Level
Describe the layers of a standard-cell power grid and why each one is there.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
The cells' own rails on met1 run along every row edge, shared between flipped neighbouring rows. Vertical met4 straps and horizontal met5 straps, alternating VDD and VSS about 27 µm apart per net, carry current across the block. Via stacks join them where same-net straps cross. Upper metals are thicker and less resistive, so the bulk current runs high.
Self-Check
Tick each key point you covered in your answer.
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CompareA Denser Grid vs Routing ResourcesL2 Mid-LevelL3 Senior
Compare halving and doubling the met4 strap pitch. What do you gain and lose?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Halving the pitch cuts IR drop and costs routing tracks; doubling it frees tracks and raises the drop. Lesson L3.5 used a 3324-cell block. There the worst drop went from 0.00148 V to 0.00069 V with half the pitch, and to 0.00332 V with double. The met4 routing resources moved from 9268 to 7880 and 9924. Measure both sides before you choose.
DC sweepDrop Along the Middle VDD Rail for Three GridsThe same placement under three met4 strap pitches: 27.14, 54.28 and 13.57 µm. - Platform grid
- met4 pitch doubled
- met4 pitch halved
Read the plot as a table
Position across the core Platform grid met4 pitch doubled met4 pitch halved 50 µm 26 µV 73.92 µV 12.54 µV 100 µm 68.53 µV 168.2 µV 24.18 µV 150 µm 158.4 µV 517.4 µV 57.41 µV 200 µm 697.3 µV 1.479 mV 414.2 µV 250 µm 96.39 µV 656.5 µV 31 µV Measured with PDNSim (the OpenROAD IR-drop tool) on one placement. A wider met4 pitch gives a deeper drop.
Self-Check
Tick each key point you covered in your answer.
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Prove ItSolve L3.5.1: Spend Fewer Straps on the GridSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
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WhyWhy Rail Drop Grows Faster Than the PitchL2 Mid-LevelL3 Senior
Why did doubling the pitch more than double the worst drop?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Between two straps, a rail with uniform load drops most at the middle, by j·r·D²/8. So that part grows with the square of the spacing D. The measured worst drop went from 0.00148 V to 0.00332 V, about 2.2 times. The rail part is only one share of the total, so the growth is less than four times.
Self-Check
Tick each key point you covered in your answer.
Misconception
"IR drop scales in proportion to the strap pitch."
The rail drop between straps grows with the square of the spacing. Doubling the pitch can more than double that part.
Source Lesson L3.5 key points
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Break ItWhat Well Taps Are ForL1 Junior
What breaks if you forget the well-tap cells?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
The n-wells and p-substrate under the cells are no longer tied to their supplies, which invites latch-up. The sky130 high-density cells have no taps inside them, so tap cells must be placed in every row. Here they sit in a checkerboard about every 14 µm. The rule comes from the process; the lesson found no public numeric tap distance to check against.
Self-Check
Tick each key point you covered in your answer.
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Prove ItSolve L3.4.1: A Connected Grid with Floating WellsSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
What People Get Wrong
Common wrong answers and why they fail.
Wrong Altitude
"Turn the power grid check off and fix it at the end."
The straps take met4 and met5 tracks, and their vias take met2 and met3. Adding them late changes routing that is already done. The grid belongs to the floorplan.
Missed Corner
"The grid connected, so every cell is powered."
Grid checks see the nets the grid knows. A missing global connection for the well pins left 27 of 27 VPB pins floating in the lesson, and the grid check still passed.
Source ASIC Point lesson L3.4 (measured build-only runs)