Crosstalk: Noise and Delay

Where the interviewer goes next. Open a node to practise that follow-up.

WhyProve ItBreak ItCompareScale It

1. Crosstalk: Noise and Delay
2. WhyWhy Switching Direction Changes the Coupling LoadL2 Mid-Level

   Why does the same coupling capacitor load the victim more when the aggressor switches the opposite way?

   Reveal the Model Answer

   The current through a capacitor follows the rate of change of the voltage across it. If both wires move the same way, the voltage across the coupling capacitor barely changes and it draws little current. If they move in opposite directions, the voltage across it swings twice as far. So the victim's driver must supply about twice the charge.

   Read the diagram as text

   • Victim driver
   • Victim wire
   • Aggressor wire
   • Receiver
   • Ground

   • Victim driver → Victim wire: drive current
   • Victim wire → Aggressor wire: C_c
   • Victim wire → Ground: C_g
   • Victim wire → Receiver: received edge

   Factors 0, 1 and 2 describe matched idealized edges. Different slopes and switching times need waveform-aware analysis.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The current through a capacitor follows the rate of change of the voltage across it. Key point 2 If both wires move the same way, the voltage across the coupling capacitor barely changes and it draws little current. Key point 3 If they move in opposite directions, the voltage across it swings twice as far. Key point 4 So the victim's driver must supply about twice the charge.

   • Lesson L6.5Crosstalk and Signal Integrity
3. CompareShielding vs Spacing a Sensitive NetL2 Mid-LevelL3 Senior

   Compare shielding a sensitive net with extra spacing.

   Reveal the Model Answer

   Spacing reduces coupling to the neighbours but costs tracks, and the gain falls off as the gap grows. A shield is a grounded or supply wire running alongside. It replaces a switching neighbour with a quiet one. So the coupling becomes a fixed load that adds delay but no noise. Clocks often get both through a non-default routing rule; ordinary signals usually just get spacing or a stronger driver.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Spacing reduces coupling to the neighbours but costs tracks, and the gain falls off as the gap grows. Key point 2 A shield is a grounded or supply wire running alongside. Key point 3 It replaces a switching neighbour with a quiet one. Key point 4 So the coupling becomes a fixed load that adds delay but no noise. Key point 5 Clocks often get both through a non-default routing rule; ordinary signals usually just get spacing or a stronger driver.

   • Lesson L6.5Crosstalk and Signal Integrity
   • Lesson L5.2Building the Tree
4. Scale ItSignal Integrity at Sign-OffL3 SeniorL4 Staff

   How would you organise signal-integrity sign-off for a large block?

   Reveal the Model Answer

   Run SI-aware timing on the extracted, routed design, with coupling kept in the parasitics. Use timing windows so only aggressors that can switch together count. Check noise glitches against receiver margins on latches, clock pins and asynchronous inputs separately from delay. Fix with spacing, shielding or driver changes, re-extract and re-check, and state which corners and activity assumptions the result covers.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Run SI-aware timing on the extracted, routed design, with coupling kept in the parasitics. Key point 2 Use timing windows so only aggressors that can switch together count. Key point 3 Check noise glitches against receiver margins on latches, clock pins and asynchronous inputs separately from delay. Key point 4 Fix with spacing, shielding or driver changes, re-extract and re-check, and state which corners and activity assumptions the result covers.

   • Lesson L6.5Crosstalk and Signal Integrity
   • Lesson L6.4Wire RC and Parasitic Extraction
   • Lesson L7.1Sign-Off Timing: Every Corner, Every Check
   • Problem L6.4.1Require the Routed Checks Together
5. Prove ItSolve L6.4.1: Require the Routed Checks TogetherSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L6.4.1

6. Break ItFixing a Hold ViolationL1 JuniorL2 Mid-Level

   Asked if they say crosstalk only slows paths

   After a setup fix that upsized a buffer, the report below shows a hold violation of -0.0207 ns that was not there before. Explain what happened and how you would fix it.

   Reveal the Model Answer

   The bigger buffer drives its 17 loads faster, so the shortest path got shorter. The capture clock is still seven buffers late. Hold lost what setup gained. Fix hold by adding delay on the short path near the capture flop, or by reducing the skew. Never fix it by touching the period. Here a smaller buf_2 meets both checks, so pick the smallest drive that closes setup rather than the biggest.

   1. At the driver

      A cell between the port and the shared net slows every path. Fine while flop S has setup slack to give.

   2. On the shared net

      Any delay here also lands on the long branch, so it costs flop S setup time.

   3. At the D pin of flop H

      Only the hold-failing path slows. It needs a cell per endpoint, but setup elsewhere is untouched.

   Read the diagram as text

   • en port: outside flop
   • shared net: fans out
   • short branch: one gate
   • long branch: deep logic
   • flop H: fails hold
   • flop S: tight setup

   • en port → shared net: data
   • shared net → short branch: data
   • shared net → long branch: data
   • short branch → flop H: D
   • long branch → flop S: D

   Where hold delay can go. Delay near the failing flop slows only the short path; delay on the shared net slows the long path too.

   The hold path after the upsize, measured with OpenSTA 3.1.0 on sky130_fd_sc_hd (our variant of the lesson L2.4 bench):

        1    0.0073    0.0818    0.3503    0.3503 ^ ff1/Q (sky130_fd_sc_hd__dfxtp_1)
       17    0.0285    0.0591    0.1220    0.4724 ^ db/X (sky130_fd_sc_hd__buf_8)
                       0.0591    0.0000    0.4724 ^ ff2/D (sky130_fd_sc_hd__dfxtp_1)
                                           0.4724   data arrival time
                       0.0353    0.0000    0.5286 ^ ff2/CLK (sky130_fd_sc_hd__dfxtp_1)
                                -0.0355    0.4931   library hold time
                                           0.4931   data required time
                                          -0.0207   slack (VIOLATED)

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The bigger buffer drives its 17 loads faster, so the shortest path got shorter. Key point 2 The capture clock is still seven buffers late. Key point 3 Hold lost what setup gained. Key point 4 Fix hold by adding delay on the short path near the capture flop, or by reducing the skew. Key point 5 Never fix it by touching the period. Key point 6 Here a smaller buf_2 meets both checks, so pick the smallest drive that closes setup rather than the biggest.

   What Interviewers Listen For (Junior)

   A good junior answer reads the report and sees that the data arrives before the late capture clock plus the hold time. It suggests adding delay on the data path.

   Misconception

   "Upsizing a cell can only help timing."

   Upsizing speeds the path, which helps setup and hurts hold. Here buf_8 turns a hold slack of +0.0745 ns into -0.0207 ns; buf_2 keeps both checks met.

   Run It

   The same path with the buffer upsized from buf_1 to buf_8 to win setup.

   create_clock -name clk -period 1.0 [get_ports clk]
   set_propagated_clock [all_clocks]
   set_input_transition 0.1 [get_ports clk]
   

   Prints: 0.4486 slack (MET) 17 0.0285 0.0591 0.1220 0.4724 ^ db/X (sky130_fd_sc_hd__buf_8) -0.0207 slack (VIOLATED)

   See the Fix

   create_clock -name clk -period 1.0 [get_ports clk]
   set_propagated_clock [all_clocks]
   set_input_transition 0.1 [get_ports clk]
   

   Prints: 0.4225 slack (MET) 0.0064 slack (MET)

   Half-Truth

   "Add delay cells anywhere on the path until hold passes."

   Delay on a net shared with long paths costs their setup too. Put it near the failing capture pin, and check setup on every path through that pin.

   Source ASIC Point lesson L5.5 (measured hold repair on the MAC)

   Wrong Altitude

   Fixes hold before clock tree synthesis, with ideal clocks.

   With ideal clocks there is no skew, so most hold failures do not exist yet. Hold is repaired after CTS, with propagated clocks.

   • Lesson L2.4Setup and Hold with Skew and Uncertainty
   • Lesson L5.5Hold Repair After CTS
   • Lesson L8.2Capstone: Diagnose Hold After CTS
   • Problem L2.4.1The Smallest Hold Repair
   • Problem L8.2.1Diagnose Hold Before Adding Cells
7. WhyWhy Hold Is Repaired After CTSL1 JuniorL2 Mid-Level

   Why do flows wait until after clock tree synthesis to repair hold?

   Reveal the Model Answer

   Hold slack depends on the real launch and capture latencies, and before CTS the clock is ideal, with zero skew. Repairing earlier would add delay for skew that may never appear and miss the skew that does. In lesson L5.5 no endpoint failed hold with ideal clocks, while 45 failed after CTS.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Hold slack depends on the real launch and capture latencies, and before CTS the clock is ideal, with zero skew. Key point 2 Repairing earlier would add delay for skew that may never appear and miss the skew that does. Key point 3 In lesson L5.5 no endpoint failed hold with ideal clocks, while 45 failed after CTS.

   • Lesson L5.5Hold Repair After CTS
   • Lesson L5.3From Ideal to Propagated Clocks
8. CompareDelay Cells vs Buffer Chains for HoldL1 JuniorL2 Mid-Level

   Compare a delay cell with a chain of small buffers as a hold fix.

   Reveal the Model Answer

   A delay cell is built to be slow. In sky130, dlygate4sd3_1 gives about 0.53 ns for 10 µm², while buf_1 gives about 0.08 ns for 3.75 µm². So one delay cell replaces several buffers at far less area per nanosecond. Buffers suit small fixes and are easier to resize later.

   ff1 → ff2hold check, earliest arrival2 cells

   • Clock latency
   • Cell delay
   • Hold time

   1. The delay cell

      hd1 adds 0.5205 ns to the fastest path.

   2. Hold met

      Hold slack 0.4835 ns.

   Read the path as a table

   Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns. Capture: clk rise edge at 0.0000 ns, latency 0.3818 ns, library hold time −0.0326 ns.

   Arrival 0.8327 ns, required 0.3492 ns, slack 0.4835 ns (met).

   Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
   1	ff1/CLK → ff1/Q	dfxtp_1	rise	0.3123	0.3123	0.0333
   	ff1/Q → hd1/A	wire q1	rise	0.0000	0.3123	0.0333
   2	hd1/A → hd1/X	dlygate4sd3_1	rise	0.5205	0.8327	0.0451
   	hd1/X → ff2/D	wire q1d	rise	0.0000	0.8327	0.0451

   The report

   Startpoint: ff1 (rising edge-triggered flip-flop clocked by clk)
   Endpoint: ff2 (rising edge-triggered flip-flop clocked by clk)
   Path Group: clk
   Path Type: min
   
   Fanout       Cap      Slew     Delay      Time   Description
   -------------------------------------------------------------------------------------
                                 0.0000    0.0000   clock clk (rise edge)
                                 0.0000    0.0000   clock source latency
        2    0.0041    0.1000    0.0000    0.0000 ^ clk (in)
                                                    clk (net)
                       0.1000    0.0000    0.0000 ^ ff1/CLK (sky130_fd_sc_hd__dfxtp_1)
        1    0.0017    0.0333    0.3123    0.3123 ^ ff1/Q (sky130_fd_sc_hd__dfxtp_1)
                                                    q1 (net)
                       0.0333    0.0000    0.3123 ^ hd1/A (sky130_fd_sc_hd__dlygate4sd3_1)
        1    0.0017    0.0451    0.5205    0.8327 ^ hd1/X (sky130_fd_sc_hd__dlygate4sd3_1)
                                                    q1d (net)
                       0.0451    0.0000    0.8327 ^ ff2/D (sky130_fd_sc_hd__dfxtp_1)
                                           0.8327   data arrival time
   
                                 0.0000    0.0000   clock clk (rise edge)
                                 0.0000    0.0000   clock source latency
        2    0.0041    0.1000    0.0000    0.0000 ^ clk (in)
                                                    clk (net)
                       0.1000    0.0000    0.0000 ^ cb1/A (sky130_fd_sc_hd__clkbuf_1)
        1    0.0022    0.0395    0.0906    0.0906 ^ cb1/X (sky130_fd_sc_hd__clkbuf_1)
                                                    ck1 (net)
                       0.0395    0.0000    0.0906 ^ cb2/A (sky130_fd_sc_hd__clkbuf_1)
        1    0.0022    0.0388    0.0736    0.1642 ^ cb2/X (sky130_fd_sc_hd__clkbuf_1)
                                                    ck2 (net)
                       0.0388    0.0000    0.1642 ^ cb3/A (sky130_fd_sc_hd__clkbuf_1)
        1    0.0022    0.0388    0.0734    0.2376 ^ cb3/X (sky130_fd_sc_hd__clkbuf_1)
                                                    ck3 (net)
                       0.0388    0.0000    0.2376 ^ cb4/A (sky130_fd_sc_hd__clkbuf_1)
        1    0.0022    0.0388    0.0734    0.3110 ^ cb4/X (sky130_fd_sc_hd__clkbuf_1)
                                                    ck4 (net)
                       0.0388    0.0000    0.3110 ^ cb5/A (sky130_fd_sc_hd__clkbuf_1)
        1    0.0019    0.0353    0.0708    0.3818 ^ cb5/X (sky130_fd_sc_hd__clkbuf_1)
                                                    ck5 (net)
                       0.0353    0.0000    0.3818 ^ ff2/CLK (sky130_fd_sc_hd__dfxtp_1)
                                 0.0000    0.3818   clock reconvergence pessimism
                                -0.0326    0.3492   library hold time
                                           0.3492   data required time
   -------------------------------------------------------------------------------------
                                           0.3492   data required time
                                          -0.8327   data arrival time
   -------------------------------------------------------------------------------------
                                           0.4835   slack (MET)

   One dlygate4sd3_1 between the two flops of lesson L2.4 turns a failing hold check into 0.4835 ns of slack.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A delay cell is built to be slow. Key point 2 In sky130, dlygate4sd3_1 gives about 0.53 ns for 10 µm², while buf_1 gives about 0.08 ns for 3.75 µm². Key point 3 So one delay cell replaces several buffers at far less area per nanosecond. Key point 4 Buffers suit small fixes and are easier to resize later.

   • Lesson L5.5Hold Repair After CTS
9. Prove ItSolve L2.4.1: The Smallest Hold RepairSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L2.4.1

10. Scale ItHold Repair Across Four CornersL2 Mid-LevelL3 Senior

    Your hold repair passes at the fast corner but fails setup at the slow corner. How do you close both?

    Reveal the Model Answer

    Repair against all required corners at once. Then the tool sees the setup cost at the slow corner when it inserts delay at the fast one. Prefer delay on paths with setup slack to spare at every corner. Fix shared skew in the clock tree before adding cells. A repair that must break setup to fix hold shows the constraints or the clock tree need work, not more cells.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 Repair against all required corners at once. Key point 2 Then the tool sees the setup cost at the slow corner when it inserts delay at the fast one. Key point 3 Prefer delay on paths with setup slack to spare at every corner. Key point 4 Fix shared skew in the clock tree before adding cells. Key point 5 A repair that must break setup to fix hold shows the constraints or the clock tree need work, not more cells.

    • Lesson L5.5Hold Repair After CTS
    • Lesson L7.1Sign-Off Timing: Every Corner, Every Check
    • Lesson L2.9Corners, Derates, OCV and CPPR
    • Problem L7.1.1Make the Hold Repair Survive Four Corners
11. Prove ItSolve L7.1.1: Make the Hold Repair Survive Four CornersSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem L7.1.1

12. Break ItOne Delay Cell for Forty Hold FixesL2 Mid-LevelL3 Senior

    Break it: the repair fixes forty hold violations with one delay cell on a shared net. What can go wrong?

    Reveal the Model Answer

    The shared net also feeds long paths, and they slow down by the same delay. With tight setup at the slow corner, those paths now fail. Put the delay near each failing D pin instead, where only the short path passes. Then check setup at every corner again.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 The shared net also feeds long paths, and they slow down by the same delay. Key point 2 With tight setup at the slow corner, those paths now fail. Key point 3 Put the delay near each failing D pin instead, where only the short path passes. Key point 4 Then check setup at every corner again.

    Half-Truth

    "One cell for forty fixes is always the best repair."

    It is the cheapest in area, but its delay lands on every path through that net. Paths with no setup margin then fail.

    Source Lesson L5.5 key points

    • Lesson L5.5Hold Repair After CTS
    • Lesson L2.9Corners, Derates, OCV and CPPR