Antenna Violations

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItCompareScale It

1. Antenna Violations
2. WhyWhy a Layer Jump Fixes an AntennaL1 Junior

   Why does moving part of a long wire up to a higher metal layer fix an antenna violation?

   Reveal the Model Answer

   The long lower-layer segment is split, and the parts are joined only when the upper layer is built. By then the path to a driving cell's diffusion exists. So the charge collected on each lower piece is limited to the short segment still attached to the gate.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The long lower-layer segment is split, and the parts are joined only when the upper layer is built. Key point 2 By then the path to a driving cell's diffusion exists. Key point 3 So the charge collected on each lower piece is limited to the short segment still attached to the gate.

   • Lesson L6.6Antenna Rules
3. CompareAntenna Diode vs Layer JumpL1 JuniorL2 Mid-Level

   Compare an antenna diode with a layer jump as the fix.

   Reveal the Model Answer

   A diode works whatever the routing, but it is a cell that needs a placement site and adds capacitance to the net. A layer jump costs no cell, only vias and upper-layer tracks, and is done by the router. Lesson L6.6 measures the cost of each on real nets; the lesson's problem asks for protection with fewer diodes.

   f0 → f1setup check, latest arrival2 cells

   • Clock latency
   • Cell delay
   • Setup time

   Read the path as a table

   Launch: clk rise edge at 0.0000 ns, clock latency 0.0000 ns (ideal). Capture: clk rise edge at 1.0000 ns, latency 0.0000 ns, library setup time −0.0849 ns.

   Arrival 0.5108 ns, required 0.9151 ns, slack 0.4044 ns (met).

   Cell	Arc	Through	Edge	Delay (ns)	Time (ns)	Slew (ns)
   1	f0/CLK → f0/Q	dfxtp_1	rise	0.3156	0.3156	0.0372
   	f0/Q → victim_driver/A	wire launch	rise	0.0000	0.3156	0.0372
   2	victim_driver/A → victim_driver/X	buf_1	rise	0.1951	0.5108	0.2146
   	victim_driver/X → f1/D	wire observe	rise	0.0000	0.5108	0.2146

   The report

   Startpoint: f0 (rising edge-triggered flip-flop clocked by clk)
   Endpoint: f1 (rising edge-triggered flip-flop clocked by clk)
   Path Group: clk
   Path Type: max
   
   Fanout       Cap      Slew     Delay      Time   Description
   -------------------------------------------------------------------------------------
                       0.1000    0.0000    0.0000   clock clk (rise edge)
                                 0.0000    0.0000   clock network delay (ideal)
                       0.1000    0.0000    0.0000 ^ f0/CLK (sky130_fd_sc_hd__dfxtp_1)
        1    0.0022    0.0372    0.3156    0.3156 ^ f0/Q (sky130_fd_sc_hd__dfxtp_1)
                                                    launch (net)
                       0.0372    0.0000    0.3156 ^ victim_driver/A (sky130_fd_sc_hd__buf_1)
        3    0.0176    0.2146    0.1951    0.5108 ^ victim_driver/X (sky130_fd_sc_hd__buf_1)
                                                    observe (net)
                       0.2146    0.0000    0.5108 ^ f1/D (sky130_fd_sc_hd__dfxtp_1)
                                           0.5108   data arrival time
   
                       0.1000    1.0000    1.0000   clock clk (rise edge)
                                 0.0000    1.0000   clock network delay (ideal)
                                 0.0000    1.0000   clock reconvergence pessimism
                                           1.0000 ^ f1/CLK (sky130_fd_sc_hd__dfxtp_1)
                                -0.0849    0.9151   library setup time
                                           0.9151   data required time
   -------------------------------------------------------------------------------------
                                           0.9151   data required time
                                          -0.5108   data arrival time
   -------------------------------------------------------------------------------------
                                           0.4044   slack (MET)

   The cost of a diode, measured: its pin capacitance enters the timing of the net it protects.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A diode works whatever the routing, but it is a cell that needs a placement site and adds capacitance to the net. Key point 2 A layer jump costs no cell, only vias and upper-layer tracks, and is done by the router. Key point 3 Lesson L6.6 measures the cost of each on real nets; the lesson's problem asks for protection with fewer diodes.

   • Lesson L6.6Antenna Rules
   • Problem L6.6.2Protect the Routes with Fewer Diodes
4. Prove ItSolve L6.6.2: Protect the Routes with Fewer DiodesSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L6.6.2

5. Scale ItRunning the Sign-Off ReviewL3 SeniorL4 Staff

   You chair the final sign-off review for a block. What must you see before you sign?

   Reveal the Model Answer

   Every check, run on one final netlist and layout. That means timing in all modes and corners, and IR, EM, DRC, LVS, antenna and equivalence. Each comes with its inputs, tool versions and pass criteria. Anything not run or waived is listed as open with an owner. A later change of geometry or logic invalidates the results it touches, so they are re-run, not carried over.

   Read the diagram as text

   • Final design revision
   • Netlist + SPEF + SDC
   • Merged layout + decks
   • Review with open items

   • Final design revision → Netlist + SPEF + SDC: timing views
   • Final design revision → Merged layout + decks: physical views
   • Netlist + SPEF + SDC → Review with open items: checks and coverage
   • Merged layout + decks → Review with open items: geometry and circuit

   A report from an earlier route does not certify shapes changed by a later ECO or fill operation.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Every check, run on one final netlist and layout. Key point 2 That means timing in all modes and corners, and IR, EM, DRC, LVS, antenna and equivalence. Key point 3 Each comes with its inputs, tool versions and pass criteria. Key point 4 Anything not run or waived is listed as open with an owner. Key point 5 A later change of geometry or logic invalidates the results it touches, so they are re-run, not carried over.

   • Lesson L7.6The Sign-Off Review
   • Lesson L8.4Capstone: RTL to a Reviewed Physical Handoff
   • Problem L8.4.1Reject an Overstated Datasheet
6. Prove ItSolve L8.4.1: Reject an Overstated DatasheetSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L8.4.1

7. What IfSigning with One Check Still UnrunL3 SeniorL4 Staff

   What if the schedule pushes you to sign while the IR-drop check has not been run on the final layout?

   Reveal the Model Answer

   List it as open, with an owner, a date and the risk it carries. The clean reports beside it do not cover it. If the team accepts the risk, record who accepted it and why, so the tape-out record shows it. Never mark an unrun check as passed.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 List it as open, with an owner, a date and the risk it carries. Key point 2 The clean reports beside it do not cover it. Key point 3 If the team accepts the risk, record who accepted it and why, so the tape-out record shows it. Key point 4 Never mark an unrun check as passed.

   Half-Truth

   "Timing and DRC are clean, so IR drop is probably fine."

   IR drop depends on currents and the grid, which neither check looks at. A clean report in one area says nothing about another.

   Source Lesson L7.6 key points

   • Lesson L7.6The Sign-Off Review
   • Lesson L3.5IR Drop and Electromigration
8. Prove ItSolve L6.6.1: Compute a Clock-Pin Antenna BudgetSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L6.6.1