Interview Question · Design
A Timing Closure Strategy for a Tight Block
- Likely at Google
- Likely at Apple
- Likely at Synopsys
The Question
The interviewer asks
You own a block at an advanced node with a tight frequency target, many corners and a fixed tape-out date. How do you plan timing closure from netlist to sign-off?
You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Start with constraints that are complete and agreed, and a floorplan that serves the critical data flow. Both are cheap to change only early. Re-time every stage against the same mode and corner set. Keep margins explicit for what later stages add: wire, clock tree, coupling, variation. Close design rules before timing and hold after CTS across all corners. Plan a sign-off review with every check, its inputs and its open items, plus a budget of ECO cycles before the freeze.
- Synthesis
Yosys maps the RTL to cells of the library: a netlist with cell types and connections, and no positions.
- Floorplan
The die and the core get their size. The core is cut into rows of sites, tap cells go in, and the power grid is drawn. No logic cell is placed yet.
- Placement
Global placement spreads the cells to keep connected cells close. Detailed placement then puts each one on a legal site in a row.
- Clock tree
The ideal clock becomes a tree of buffers. Each flop now sees the edge at its own time, and that difference is skew.
- Routing
Global routing plans each net through regions and layers. Detailed routing draws every wire and via on the routing grid.
- Sign-off
Extract the resistance and capacitance of every wire, time the design again, check the drawing against the rules, and write the GDSII file for the foundry.
Read the diagram as text
- Synthesis: RTL to library cells
- Floorplan: Die, rows, taps, power grid
- Placement: A legal site for every cell
- Clock tree: Buffers from the clock pin to every flop
- Routing: Every wire on metal
- Sign-off: Extract, time, check, write GDSII
- Synthesis → Floorplan: netlist
- Floorplan → Placement: empty rows
- Placement → Clock tree: placed cells
- Clock tree → Routing: clock tree
- Routing → Sign-off: routed nets
Each stage swaps an estimate for a real model. Check timing after every stage, and keep a margin for the stages still to come.
Self-Check
Tick each key point you covered in your answer.
What Interviewers Listen For (Senior)
A good senior answer puts the stages in order: constraints, floorplan, placement, CTS and routing. It checks timing after each one, and writes down the margin kept for each stage.
What Interviewers Listen For (Staff)
A good staff answer turns the plan into a schedule with exit criteria for every stage. It agrees the corner strategy with the library team. It adds a route back to RTL for paths no tool can fix, and an ECO budget before the freeze.
Cross-Questions
Where the interviewer goes next. Open a node to practise that follow-up.
WhyWhat IfProve ItCompareScale It
- A Timing Closure Strategy for a Tight Block
-
WhyWhy Each Stage Needs Its Own MarginL2 Mid-LevelL3 Senior
Why does a block that meets timing after placement often fail after routing?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Each stage replaces an estimate with a real model. Placement adds estimated wire, and CTS replaces the ideal clock with real latencies and slews. Routing replaces estimated wire with detoured, coupled wire. In lesson L1.1 the same path lost about 0.31 ns from global routing alone. So the target at each stage must leave room for what comes next.
Self-Check
Tick each key point you covered in your answer.
-
CompareFlat Derates vs Depth-Aware VariationL3 Senior
Compare a flat OCV derate with depth- and distance-aware or statistical variation models.
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
A flat derate applies the same percentage to every cell. That is pessimistic on deep paths, where random variation partly cancels, and can be optimistic on short ones. Depth- and distance-aware tables scale the derate with the number of stages and the spread of the path. Statistical models carry a sigma per cell arc and combine them along the path. All of them need data from the library; the method is only as good as that data.
Self-Check
Tick each key point you covered in your answer.
-
What IfWhen a Path Goes Back to RTLL3 Senior
Asked if they assume every path can be fixed in the flow
A path still fails by 15 % of the period after every physical fix. What do you do?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Stop spending flow iterations on it. Take it to the RTL owner with the evidence: the path, its logic depth and the best slack each fix reached. The structural options are pipelining, retiming, or restructuring the logic, each with a cost in latency or verification. Agree on it early, because an RTL change late in the schedule restarts synthesis, equivalence and the flow.
Self-Check
Tick each key point you covered in your answer.
-
ComparePipelining Versus Retiming as the RTL FixL3 Senior
Compare pipelining with retiming as the fix. What does each one cost the verification team?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Pipelining adds a register stage, so latency grows by a cycle. Every interface, model and test that counts cycles must change. Retiming moves existing registers and keeps the latency at the ports. But the internal flops no longer match the RTL, so equivalence needs a sequential check.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"Retiming is free; the tool just does it."
It changes which flops exist. Combinational equivalence cannot map them, and debug sees different internal state.
-
Scale ItRunning the Sign-Off ReviewL3 SeniorL4 Staff
You chair the final sign-off review for a block. What must you see before you sign?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
Every check, run on one final netlist and layout. That means timing in all modes and corners, and IR, EM, DRC, LVS, antenna and equivalence. Each comes with its inputs, tool versions and pass criteria. Anything not run or waived is listed as open with an owner. A later change of geometry or logic invalidates the results it touches, so they are re-run, not carried over.
One Final Revision Feeds Distinct ChecksMatching views preserve the relationship between implementation and results. Read the diagram as text
- Final design revision
- Netlist + SPEF + SDC
- Merged layout + decks
- Review with open items
- Final design revision → Netlist + SPEF + SDC: timing views
- Final design revision → Merged layout + decks: physical views
- Netlist + SPEF + SDC → Review with open items: checks and coverage
- Merged layout + decks → Review with open items: geometry and circuit
A report from an earlier route does not certify shapes changed by a later ECO or fill operation.
Self-Check
Tick each key point you covered in your answer.
-
Prove ItSolve L8.4.1: Reject an Overstated DatasheetSimulator-graded
Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
-
What IfSigning with One Check Still UnrunL3 SeniorL4 Staff
What if the schedule pushes you to sign while the IR-drop check has not been run on the final layout?
2:30You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.
Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
You can edit your answer before you send it. Feedback uses AI and checks your answer only against our written answer. No credits are used and your answer is not saved.
Reveal the Model Answer
List it as open, with an owner, a date and the risk it carries. The clean reports beside it do not cover it. If the team accepts the risk, record who accepted it and why, so the tape-out record shows it. Never mark an unrun check as passed.
Self-Check
Tick each key point you covered in your answer.
Half-Truth
"Timing and DRC are clean, so IR drop is probably fine."
IR drop depends on currents and the grid, which neither check looks at. A clean report in one area says nothing about another.
Source Lesson L7.6 key points
What People Get Wrong
Common wrong answers and why they fail.
Wrong Altitude
"Run the flow, then fix whatever fails at the end."
Late fixes are the most expensive and the least effective. Constraint holes and a poor floorplan found at sign-off cost a respin of the whole flow.
Missed Corner
"Positive slack at the typical corner after placement means we are on track."
Every later stage adds delay or variation. In lesson L1.1 one MAC went from +0.70 ns at floorplan to -0.18 ns after global routing, at one corner only.
Source ASIC Point lesson L1.1 (measured stage-by-stage WNS)
Delivery
Lists tool commands without saying how progress is measured.
A strategy needs exit criteria: WNS and TNS per stage, failing-endpoint counts, design-rule counts and open sign-off items, tracked against the schedule.