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Interview Question · Concept

AHB Bursts and the 1 KB Rule

L1 JuniorL2 Mid-Levelahbbursts

The Question

The interviewer asks

List the AHB burst types. Where does a WRAP4 of words starting at 0x34 go, and what rule must an incrementing burst respect?

Reveal the Model Answer

HBURST gives SINGLE, undefined-length INCR, and fixed INCR4/8/16 and WRAP4/8/16. The number counts beats, not bytes. A wrapping burst wraps inside a window of beats times size. So a WRAP4 of words from 0x34 visits 0x34, 0x38, 0x3C, 0x30. An incrementing burst must not cross a 1 KB boundary, because subordinate regions are at least 1 KB and 1 KB aligned. Every beat is aligned to its size.

A WRAP8 Burst from 0x34 Lands in MemoryMeasured: cycle 0 is edge 4, where the first address phase is accepted. beat_addr is the address of the beat in its data phase; dphase is 1 while a write beat is in its data phase.
HADDRHWDATAManagerWRAP8 of wordsMemory 0x20 to 0x3flane01230x200x240x280x2c0x300x340x380x3c

Each cell is one byte; lane 0 is the lowest address of its row. The pill carries the data of the beat.

012345678clkhtransNONSEQSEQIDLEhaddr34383c2024282c30dphasebeat_addrx34383c2024282c30hwdata0a0a1a2a3a4a5a6a7hwstrb00001111hready
  1. Cycle 0

    NONSEQ at 0x34 starts the burst. Eight beats of 4 bytes make a 32-byte window, 0x34 rounded down to 32 is 0x20: the burst stays inside 0x20 to 0x3f.

  2. Cycle 1

    Beat 0's data lands at 0x34 while beat 1's address, 0x38, is already on the bus: the pipeline of P4.2, one beat at a time.

  3. Cycle 3

    After 0x3c the next address would be 0x40, the end of the window, so the manager drives 0x20. The data moving now is beat 2, for 0x3c.

  4. Cycle 4

    Beat 3 lands at 0x20, the first row of the window.

  5. Cycle 8

    Beat 7 lands at 0x30 and the bus goes IDLE. All eight rows are written: from 0x20 the dump reads a3 a4 a5 a6 a7 a0 a1 a2.

Measured: a WRAP8 of words from 0x34. After 0x3c it wraps to 0x20, inside its 32-byte window.

Self-Check

Tick each key point you covered in your answer.

What Interviewers Listen For (Junior)

A good junior answer lists the HBURST types and works out the wrap addresses. It states the 1 KB rule and the reason for it.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompare

  1. AHB Bursts and the 1 KB Rule
  2. WhyWhy the 1 KB BoundaryL1 JuniorL2 Mid-Level

    Why must an AHB incrementing burst not cross a 1 KB boundary? And how does that compare with AXI?

    Reveal the Model Answer

    Subordinate regions are at least 1 KB, and they start and end on 1 KB boundaries. So a burst that stays inside one 1 KB block never changes subordinate mid-burst. Subordinates can then treat SEQ beats as a continuation without decoding again. AXI applies the same idea with a 4 KB boundary. A wrapping burst stays inside its own aligned window, which on usual bus widths is far smaller than 1 KB.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer links the rule to the smallest subordinate region and its 1 KB boundaries.

  3. Break ItAn INCR Burst Across a 1 KB BoundaryL1 JuniorL2 Mid-Level

    Break it: an INCR4 burst of words starts at 0x3F8. What goes wrong at the boundary, and what should the manager do?

    Reveal the Model Answer

    The beats are 0x3F8, 0x3FC, 0x400 and 0x404. The third beat starts the next 1 KB block, which may belong to another subordinate. That subordinate sees a SEQ beat with no NONSEQ before it. The manager must split the request: two beats, then a new NONSEQ at 0x400.

    Self-Check

    Tick each key point you covered in your answer.

    Misconception

    "The decoder looks at every beat, so it handles the crossing."

    It does select the new subordinate. But that subordinate gets a SEQ beat it never saw start, and SEQ means continue your burst.

    Source AMBA AHB Protocol Specification IHI 0033C §4.2 Address decoding

  4. Prove ItNext Address in a Wrapping BurstL1 JuniorL2 Mid-Level

    Write the next-address function for AHB bursts, wrapping and incrementing, and show it on the spec's examples.

    Reveal the Model Answer

    The window is beats times size, aligned to its own size. Add the size to the address. For a wrapping burst, if that reaches the end of the window, go back to the window's base. The run reproduces the specification's WRAP4, INCR4, WRAP8 and halfword INCR8 examples. The classic bug is a window sized for the old burst length, which turns WRAP8 back at 16 bytes.

    RUNIcarus Verilog · in your browser
    Edit the code, then run it
    Expected: WRAP4 words from 0x34: 34 38 3c 30 INCR4 words from 0x38: 38 3c 40 44 WRAP8 words from 0x34: 34 38 3c 20 24 28 2c 30 INCR8 halfwords from 0x34: 34 36 38 3a 3c 3e 40 42

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer works out the wrap window from the beat count and size, and aligns it.

  5. What IfBursts That End EarlyL2 Mid-LevelL3 Senior

    Can an AHB burst end before its last beat? Who may end it, and what must a subordinate tolerate?

    Reveal the Model Answer

    A manager may not end a fixed-length burst on its own, but two things can end it. After an ERROR, the manager may cancel the remaining beats. A multi-layer interconnect may also cut a burst to serve another manager. An INCR burst also ends whenever BUSY is followed by IDLE or NONSEQ. Subordinates must work correctly when a burst never completes, for example by dropping prefetched data.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer names both causes of an early end, an ERROR and a multi-layer interconnect, plus the INCR case.

  6. CompareAHB Pipelining Against AXI Outstanding TransactionsL1 JuniorL2 Mid-Level

    Compare AHB's pipelining with AXI's outstanding transactions. When would you still pick AHB?

    Reveal the Model Answer

    AHB has one address and control path, with at most one transfer in address and one in data. Transfers complete in order, and a wait state stalls whatever is behind it. AXI has independent channels and IDs, so a manager can issue many requests without waiting. Responses with different IDs may return out of order. AHB wins on area and simplicity for a single manager with modest latency, such as a microcontroller memory bus.

    Self-Check

    Tick each key point you covered in your answer.

    What Interviewers Listen For (Junior)

    A good junior answer contrasts the two buses. AHB is two transfers deep and in order, while AXI allows many requests in flight, ordered by ID.

  7. Prove ItSolve P4.6.2: WRAP8Simulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P4.6.2

What People Get Wrong

Common wrong answers and why they fail.

Misconception

INCR4 moves four bytes.

The number is beats. The bytes are beats times the HSIZE transfer size: 16 bytes for an INCR4 of words.

Source AMBA AHB Protocol Specification IHI 0033C §3.6 Burst operation (Note)

Spec Misquote

An AHB burst can start at an unaligned address, like AXI.

Every transfer of an AHB burst must be aligned to its size: words on word boundaries, halfwords on halfword boundaries. Unaligned data becomes smaller aligned transfers.

Source AMBA AHB Protocol Specification IHI 0033C §3.6 Burst operation

Spec Misquote

A fixed-length burst may end with BUSY when the manager runs out of data.

INCR4/8/16 and WRAP4/8/16 must end with a SEQ beat. Only an undefined-length INCR may end after BUSY.

Source AMBA AHB Protocol Specification IHI 0033C §3.6.1 Burst termination after a BUSY transfer

Learn It, Then Prove It