AHB Decoder, Multiplexor and Default Subordinate

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompareScale It

1. AHB Decoder, Multiplexor and Default Subordinate
2. WhyAHB Bursts and the 1 KB RuleL1 JuniorL2 Mid-Level

   List the AHB burst types. Where does a WRAP4 of words starting at 0x34 go, and what rule must an incrementing burst respect?

   Reveal the Model Answer

   HBURST gives SINGLE, undefined-length INCR, and fixed INCR4/8/16 and WRAP4/8/16. The number counts beats, not bytes. A wrapping burst wraps inside a window of beats times size. So a WRAP4 of words from 0x34 visits 0x34, 0x38, 0x3C, 0x30. An incrementing burst must not cross a 1 KB boundary, because subordinate regions are at least 1 KB and 1 KB aligned. Every beat is aligned to its size.

   Each cell is one byte; lane 0 is the lowest address of its row. The pill carries the data of the beat.

   1. Cycle 0

      NONSEQ at 0x34 starts the burst. Eight beats of 4 bytes make a 32-byte window, 0x34 rounded down to 32 is 0x20: the burst stays inside 0x20 to 0x3f.

   2. Cycle 1

      Beat 0's data lands at 0x34 while beat 1's address, 0x38, is already on the bus: the pipeline of P4.2, one beat at a time.

   3. Cycle 3

      After 0x3c the next address would be 0x40, the end of the window, so the manager drives 0x20. The data moving now is beat 2, for 0x3c.

   4. Cycle 4

      Beat 3 lands at 0x20, the first row of the window.

   5. Cycle 8

      Beat 7 lands at 0x30 and the bus goes IDLE. All eight rows are written: from 0x20 the dump reads a3 a4 a5 a6 a7 a0 a1 a2.

   Measured: a WRAP8 of words from 0x34. After 0x3c it wraps to 0x20, inside its 32-byte window.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 HBURST gives SINGLE, undefined-length INCR, and fixed INCR4/8/16 and WRAP4/8/16. Key point 2 The number counts beats, not bytes. Key point 3 A wrapping burst wraps inside a window of beats times size. Key point 4 So a WRAP4 of words from 0x34 visits 0x34, 0x38, 0x3C, 0x30. Key point 5 An incrementing burst must not cross a 1 KB boundary, because subordinate regions are at least 1 KB and 1 KB aligned. Key point 6 Every beat is aligned to its size.

   What Interviewers Listen For (Junior)

   A good junior answer lists the HBURST types and works out the wrap addresses. It states the 1 KB rule and the reason for it.

   Misconception

   INCR4 moves four bytes.

   The number is beats. The bytes are beats times the HSIZE transfer size: 16 bytes for an INCR4 of words.

   Source AMBA AHB Protocol Specification IHI 0033C §3.6 Burst operation (Note)

   Spec Misquote

   An AHB burst can start at an unaligned address, like AXI.

   Every transfer of an AHB burst must be aligned to its size: words on word boundaries, halfwords on halfword boundaries. Unaligned data becomes smaller aligned transfers.

   Source AMBA AHB Protocol Specification IHI 0033C §3.6 Burst operation

   Spec Misquote

   A fixed-length burst may end with BUSY when the manager runs out of data.

   INCR4/8/16 and WRAP4/8/16 must end with a SEQ beat. Only an undefined-length INCR may end after BUSY.

   Source AMBA AHB Protocol Specification IHI 0033C §3.6.1 Burst termination after a BUSY transfer

   • Lesson P4.6Bursts: The Address of Every Beat
   • Lesson P4.3HTRANS: IDLE, BUSY, NONSEQ, SEQ
   • Problem P4.6.1The Beat Generator
   • Problem P4.6.2WRAP8
3. WhyWhy the 1 KB BoundaryL1 JuniorL2 Mid-Level

   Why must an AHB incrementing burst not cross a 1 KB boundary? And how does that compare with AXI?

   Reveal the Model Answer

   Subordinate regions are at least 1 KB, and they start and end on 1 KB boundaries. So a burst that stays inside one 1 KB block never changes subordinate mid-burst. Subordinates can then treat SEQ beats as a continuation without decoding again. AXI applies the same idea with a 4 KB boundary. A wrapping burst stays inside its own aligned window, which on usual bus widths is far smaller than 1 KB.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Subordinate regions are at least 1 KB, and they start and end on 1 KB boundaries. Key point 2 So a burst that stays inside one 1 KB block never changes subordinate mid-burst. Key point 3 Subordinates can then treat SEQ beats as a continuation without decoding again. Key point 4 AXI applies the same idea with a 4 KB boundary. Key point 5 A wrapping burst stays inside its own aligned window, which on usual bus widths is far smaller than 1 KB.

   What Interviewers Listen For (Junior)

   A good junior answer links the rule to the smallest subordinate region and its 1 KB boundaries.

   • Lesson P4.6Bursts: The Address of Every Beat
   • Lesson P4.8Decoder, Multiplexor and the Default Subordinate
   • Lesson P2.6Bursts and the Address of Every Beat
   • Problem P4.8.2Decoder and Default Subordinate
4. Break ItAn INCR Burst Across a 1 KB BoundaryL1 JuniorL2 Mid-Level

   Break it: an INCR4 burst of words starts at 0x3F8. What goes wrong at the boundary, and what should the manager do?

   Reveal the Model Answer

   The beats are 0x3F8, 0x3FC, 0x400 and 0x404. The third beat starts the next 1 KB block, which may belong to another subordinate. That subordinate sees a SEQ beat with no NONSEQ before it. The manager must split the request: two beats, then a new NONSEQ at 0x400.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The beats are 0x3F8, 0x3FC, 0x400 and 0x404. Key point 2 The third beat starts the next 1 KB block, which may belong to another subordinate. Key point 3 That subordinate sees a SEQ beat with no NONSEQ before it. Key point 4 The manager must split the request: two beats, then a new NONSEQ at 0x400.

   Misconception

   "The decoder looks at every beat, so it handles the crossing."

   It does select the new subordinate. But that subordinate gets a SEQ beat it never saw start, and SEQ means continue your burst.

   Source AMBA AHB Protocol Specification IHI 0033C §4.2 Address decoding

   • Lesson P4.6Bursts: The Address of Every Beat
   • Problem P4.8.2Decoder and Default Subordinate
5. Prove ItNext Address in a Wrapping BurstL1 JuniorL2 Mid-Level

   Write the next-address function for AHB bursts, wrapping and incrementing, and show it on the spec's examples.

   Reveal the Model Answer

   The window is beats times size, aligned to its own size. Add the size to the address. For a wrapping burst, if that reaches the end of the window, go back to the window's base. The run reproduces the specification's WRAP4, INCR4, WRAP8 and halfword INCR8 examples. The classic bug is a window sized for the old burst length, which turns WRAP8 back at 16 bytes.

   RUNIcarus Verilog · in your browser

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: WRAP4 words from 0x34: 34 38 3c 30 INCR4 words from 0x38: 38 3c 40 44 WRAP8 words from 0x34: 34 38 3c 20 24 28 2c 30 INCR8 halfwords from 0x34: 34 36 38 3a 3c 3e 40 42

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The window is beats times size, aligned to its own size. Key point 2 Add the size to the address. Key point 3 For a wrapping burst, if that reaches the end of the window, go back to the window's base. Key point 4 The run reproduces the specification's WRAP4, INCR4, WRAP8 and halfword INCR8 examples. Key point 5 The classic bug is a window sized for the old burst length, which turns WRAP8 back at 16 bytes.

   What Interviewers Listen For (Junior)

   A good junior answer works out the wrap window from the beat count and size, and aligns it.

   • Lesson P4.6Bursts: The Address of Every Beat
   • Problem P4.6.1The Beat Generator
   • Problem P4.6.2WRAP8
6. What IfBursts That End EarlyL2 Mid-LevelL3 Senior

   Can an AHB burst end before its last beat? Who may end it, and what must a subordinate tolerate?

   Reveal the Model Answer

   A manager may not end a fixed-length burst on its own, but two things can end it. After an ERROR, the manager may cancel the remaining beats. A multi-layer interconnect may also cut a burst to serve another manager. An INCR burst also ends whenever BUSY is followed by IDLE or NONSEQ. Subordinates must work correctly when a burst never completes, for example by dropping prefetched data.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 A manager may not end a fixed-length burst on its own, but two things can end it. Key point 2 After an ERROR, the manager may cancel the remaining beats. Key point 3 A multi-layer interconnect may also cut a burst to serve another manager. Key point 4 An INCR burst also ends whenever BUSY is followed by IDLE or NONSEQ. Key point 5 Subordinates must work correctly when a burst never completes, for example by dropping prefetched data.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer names both causes of an early end, an ERROR and a multi-layer interconnect, plus the INCR case.

   • Lesson P4.5The Two-Cycle ERROR
   • Lesson P4.6Bursts: The Address of Every Beat
   • Problem P4.12.1Catch Every Broken Subordinate
7. CompareAHB Pipelining Against AXI Outstanding TransactionsL1 JuniorL2 Mid-Level

   Compare AHB's pipelining with AXI's outstanding transactions. When would you still pick AHB?

   Reveal the Model Answer

   AHB has one address and control path, with at most one transfer in address and one in data. Transfers complete in order, and a wait state stalls whatever is behind it. AXI has independent channels and IDs, so a manager can issue many requests without waiting. Responses with different IDs may return out of order. AHB wins on area and simplicity for a single manager with modest latency, such as a microcontroller memory bus.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 AHB has one address and control path, with at most one transfer in address and one in data. Key point 2 Transfers complete in order, and a wait state stalls whatever is behind it. Key point 3 AXI has independent channels and IDs, so a manager can issue many requests without waiting. Key point 4 Responses with different IDs may return out of order. Key point 5 AHB wins on area and simplicity for a single manager with modest latency, such as a microcontroller memory bus.

   What Interviewers Listen For (Junior)

   A good junior answer contrasts the two buses. AHB is two transfers deep and in order, while AXI allows many requests in flight, ordered by ID.

   • Lesson P4.1AHB in One Picture
   • Lesson P2.5Outstanding Transactions and Throughput
   • Lesson P2.10IDs and Same-ID Order: Why Responses Come Back in Order
8. Prove ItSolve P4.6.2: WRAP8Simulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem P4.6.2

9. Scale ItFrom One AHB Manager to SeveralL3 SeniorL4 Staff

   Now a DMA engine joins the CPU on the same subordinates. What changes in the AHB system, and what does the verification plan add?

   Reveal the Model Answer

   An interconnect adds arbitration and routing, because the AHB interface itself stays single-manager. It stalls a waiting manager by holding its HREADY low. A multi-layer interconnect may cut a burst short to serve another manager, so subordinates must cope with unfinished bursts. Locked sequences need HMASTLOCK, and exclusives need HMASTER to tell managers apart. The plan adds per-port checkers, routing scoreboards, fairness coverage and terminated-burst coverage.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 An interconnect adds arbitration and routing, because the AHB interface itself stays single-manager. Key point 2 It stalls a waiting manager by holding its HREADY low. Key point 3 A multi-layer interconnect may cut a burst short to serve another manager, so subordinates must cope with unfinished bursts. Key point 4 Locked sequences need HMASTLOCK, and exclusives need HMASTER to tell managers apart. Key point 5 The plan adds per-port checkers, routing scoreboards, fairness coverage and terminated-burst coverage.

   What Interviewers Listen For (Senior)

   A good senior answer knows several AHB managers need an interconnect. It says the interconnect stalls a manager through HREADY and may end a burst early.

   • Lesson P4.1AHB in One Picture
   • Lesson P4.8Decoder, Multiplexor and the Default Subordinate
   • Lesson P4.9Locked Transfers, Protection and Exclusive Access
   • Problem P4.9.1An Exclusive Access Monitor
10. Break ItInterconnect Bugs That Pass Block TestsL2 Mid-LevelL3 Senior

    Every subordinate passes its own block-level tests, yet the SoC sometimes reads wrong data. Which interconnect bugs slip past block tests, and what traffic exposes them?

    Illustrative integration-test excerpt
    Subordinate A unit tests: pass
    Subordinate B unit tests: pass
    SoC read A, then read B with wait states:
    read B returned data expected from A; response OKAY

    Reveal the Model Answer

    These bugs need two subordinates at once. A mux select on the wrong phase shows only on back-to-back accesses to different subordinates. A HREADY fan-in that forwards the wrong HREADYOUT shows only when one subordinate waits while another is addressed. A region off-by-one shows only at a 1 KB edge, and a one-cycle default-subordinate error only on unmapped accesses. Expose them with back-to-back cross-subordinate traffic, random waits and address sweeps at every region boundary.

    data_sel is the subordinate in the data phase: the one the multiplexor should listen to.

    1. Cycle 0

       The read of 0x0100 is in its address phase. The decoder selects m0.

    2. Cycle 1

       Its data phase ends here, and m0 is answering. But the address phase now names 0x1100, so the broken multiplexor passes m1's HRDATA: 00000000.

    3. Cycle 2

       The read of 0x1100 ends. The address phase names m0 again, and the multiplexor hands over m0's word, 0a0a0a0a.

    4. Cycle 3

       The second read of 0x0100 gets m1's 1b1b1b1b. Every read so far has the data of the one before it.

    5. Cycle 4

       Only the last read comes back right, because no new address phase follows it.

    Measured. A multiplexor keyed by the address-phase select returns each read the data of the read before it. No wire rule fires.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 These bugs need two subordinates at once. Key point 2 A mux select on the wrong phase shows only on back-to-back accesses to different subordinates. Key point 3 A HREADY fan-in that forwards the wrong HREADYOUT shows only when one subordinate waits while another is addressed. Key point 4 A region off-by-one shows only at a 1 KB edge, and a one-cycle default-subordinate error only on unmapped accesses. Key point 5 Expose them with back-to-back cross-subordinate traffic, random waits and address sweeps at every region boundary.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer names the cases that need two subordinates at once. It names the traffic that reaches them.

    • Lesson P4.8Decoder, Multiplexor and the Default Subordinate
    • Lesson P4.12Capstone: AHB Bug Hunts
    • Problem P4.12.3The Read That Returned Its Neighbour's Data
    • Problem P4.8.1The Mux
11. Prove ItSolve P4.12.3: The Read That Returned Its Neighbour's DataSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P4.12.3

12. Prove ItSolve P4.8.2: Decoder and Default SubordinateSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P4.8.2