Utilization, Aspect Ratio and Die Size

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompare

1. Utilization, Aspect Ratio and Die Size
2. WhyWhy the Core Snaps to Rows and SitesL0 FresherL1 Junior

   Why does the tool move your requested core edges slightly?

   Reveal the Model Answer

   Standard cells sit in rows of a fixed height and on sites of a fixed width, 2.72 by 0.46 µm for sky130 high density. The core must hold a whole number of rows and sites, so its corners snap to that grid. The log prints a message when it does. That is also why the effective utilization differs a little from the target.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Standard cells sit in rows of a fixed height and on sites of a fixed width, 2.72 by 0.46 µm for sky130 high density. Key point 2 The core must hold a whole number of rows and sites, so its corners snap to that grid. Key point 3 The log prints a message when it does. Key point 4 That is also why the effective utilization differs a little from the target.

   • Lesson L1.5Rows, Sites, Tracks and the Metal Stack
   • Lesson L3.1Die, Core, Utilization and Aspect Ratio
3. Prove ItSolve L3.1.1: A Floorplan After SnappingSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L3.1.1

4. What IfChanging the Aspect RatioL1 Junior

   What happens if you make the core four times taller than it is wide?

   Reveal the Model Answer

   Nets get stretched along the long side, so wirelength grows, and the short edges have less room for pins. In lesson L3.1 the same FIFO at 70 % went from 32 rows of 193 sites to 65 rows of 96 sites. Placed wirelength rose from about 6807 to 7207 µm. Pick the aspect ratio from the pin and macro plan, not by default.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Nets get stretched along the long side, so wirelength grows, and the short edges have less room for pins. Key point 2 In lesson L3.1 the same FIFO at 70 % went from 32 rows of 193 sites to 65 rows of 96 sites. Key point 3 Placed wirelength rose from about 6807 to 7207 µm. Key point 4 Pick the aspect ratio from the pin and macro plan, not by default.

   • Lesson L3.1Die, Core, Utilization and Aspect Ratio
5. CompareTarget Density vs UtilizationL1 Junior

   Compare core utilization with the placer's target density.

   Reveal the Model Answer

   Utilization is one number for the whole core: cell area over core area, fixed by the floorplan. Target density is a local goal the placer pushes every region toward, so it controls how tightly cells cluster within that core. A 40 % core can be placed at density 0.6 or 0.95, with very different wire and congestion.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Utilization is one number for the whole core: cell area over core area, fixed by the floorplan. Key point 2 Target density is a local goal the placer pushes every region toward, so it controls how tightly cells cluster within that core. Key point 3 A 40 % core can be placed at density 0.6 or 0.95, with very different wire and congestion.

   • Lesson L4.2Density and Congestion
   • Lesson L3.1Die, Core, Utilization and Aspect Ratio
6. Break ItA Power Grid That Will Not BuildL1 JuniorL2 Mid-Level

   Asked if they push utilization very high

   Your floorplan stops in power-grid generation with the error shown in the answer. What does it mean, and what are your options?

   Reveal the Model Answer

   The core is 28.52 µm wide. But one pair of met4 straps needs a 13.6 µm offset plus 15.2 µm of strap width, about 28.7 µm. So the grid cannot fit even once. Widen the core by lowering utilization or changing the aspect ratio. Or use a grid definition with narrower straps or a smaller offset for small blocks. The grid is part of the floorplan, not something added after it.

   Read the diagram as text

   • met5 strap: The block's VDD pins
   • via4: met5 to met4
   • met4 strap: Vertical, 1.6 µm wide
   • Via stack: via3, via2, via
   • met1 rail: 0.48 µm wide
   • Cell: VPWR pin

   • met5 strap → via4
   • via4 → met4 strap
   • met4 strap → Via stack
   • Via stack → met1 rail
   • met1 rail → Cell

   The grid in this error, from the top: met5 and met4 straps, via stacks, then the met1 rail of each row.

   [ERROR PDN-0185] Insufficient width (28.52 um) to add straps on layer met4 in grid "grid" with total strap width 15.2 um and offset 13.6 um.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The core is 28.52 µm wide. Key point 2 But one pair of met4 straps needs a 13.6 µm offset plus 15.2 µm of strap width, about 28.7 µm. Key point 3 So the grid cannot fit even once. Key point 4 Widen the core by lowering utilization or changing the aspect ratio. Key point 5 Or use a grid definition with narrower straps or a smaller offset for small blocks. Key point 6 The grid is part of the floorplan, not something added after it.

   What Interviewers Listen For (Junior)

   A good junior answer reads the numbers in the error message. It sees that the core is narrower than one pair of straps, and suggests a wider core.

   Wrong Altitude

   "Turn the power grid check off and fix it at the end."

   The straps take met4 and met5 tracks, and their vias take met2 and met3. Adding them late changes routing that is already done. The grid belongs to the floorplan.

   Missed Corner

   "The grid connected, so every cell is powered."

   Grid checks see the nets the grid knows. A missing global connection for the well pins left 27 of 27 VPB pins floating in the lesson, and the grid check still passed.

   Source ASIC Point lesson L3.4 (measured build-only runs)

   • Lesson L3.4The Power Grid and Well Taps
   • Lesson L1.6Reading a Flow Log
   • Problem L3.4.1A Connected Grid with Floating Wells
7. WhyHow the sky130 Power Grid Is BuiltL1 JuniorL2 Mid-Level

   Describe the layers of a standard-cell power grid and why each one is there.

   Reveal the Model Answer

   The cells' own rails on met1 run along every row edge, shared between flipped neighbouring rows. Vertical met4 straps and horizontal met5 straps, alternating VDD and VSS about 27 µm apart per net, carry current across the block. Via stacks join them where same-net straps cross. Upper metals are thicker and less resistive, so the bulk current runs high.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The cells' own rails on met1 run along every row edge, shared between flipped neighbouring rows. Key point 2 Vertical met4 straps and horizontal met5 straps, alternating VDD and VSS about 27 µm apart per net, carry current across the block. Key point 3 Via stacks join them where same-net straps cross. Key point 4 Upper metals are thicker and less resistive, so the bulk current runs high.

   • Lesson L3.4The Power Grid and Well Taps
   • Lesson L1.5Rows, Sites, Tracks and the Metal Stack
8. CompareA Denser Grid vs Routing ResourcesL2 Mid-LevelL3 Senior

   Compare halving and doubling the met4 strap pitch. What do you gain and lose?

   Reveal the Model Answer

   Halving the pitch cuts IR drop and costs routing tracks; doubling it frees tracks and raises the drop. Lesson L3.5 used a 3324-cell block. There the worst drop went from 0.00148 V to 0.00069 V with half the pitch, and to 0.00332 V with double. The met4 routing resources moved from 9268 to 7880 and 9924. Measure both sides before you choose.

   • Platform grid
   • met4 pitch doubled
   • met4 pitch halved

   Read the plot as a table

   Position across the core	Platform grid	met4 pitch doubled	met4 pitch halved
   50 µm	26 µV	73.92 µV	12.54 µV
   100 µm	68.53 µV	168.2 µV	24.18 µV
   150 µm	158.4 µV	517.4 µV	57.41 µV
   200 µm	697.3 µV	1.479 mV	414.2 µV
   250 µm	96.39 µV	656.5 µV	31 µV

   Measured with PDNSim (the OpenROAD IR-drop tool) on one placement. A wider met4 pitch gives a deeper drop.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Halving the pitch cuts IR drop and costs routing tracks; doubling it frees tracks and raises the drop. Key point 2 Lesson L3.5 used a 3324-cell block. Key point 3 There the worst drop went from 0.00148 V to 0.00069 V with half the pitch, and to 0.00332 V with double. Key point 4 The met4 routing resources moved from 9268 to 7880 and 9924. Key point 5 Measure both sides before you choose.

   • Lesson L3.5IR Drop and Electromigration
   • Lesson L3.4The Power Grid and Well Taps
   • Problem L3.5.1Spend Fewer Straps on the Grid
9. Prove ItSolve L3.5.1: Spend Fewer Straps on the GridSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem L3.5.1

10. WhyWhy Rail Drop Grows Faster Than the PitchL2 Mid-LevelL3 Senior

    Why did doubling the pitch more than double the worst drop?

    Reveal the Model Answer

    Between two straps, a rail with uniform load drops most at the middle, by j·r·D²/8. So that part grows with the square of the spacing D. The measured worst drop went from 0.00148 V to 0.00332 V, about 2.2 times. The rail part is only one share of the total, so the growth is less than four times.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 Between two straps, a rail with uniform load drops most at the middle, by j·r·D²/8. Key point 2 So that part grows with the square of the spacing D. Key point 3 The measured worst drop went from 0.00148 V to 0.00332 V, about 2.2 times. Key point 4 The rail part is only one share of the total, so the growth is less than four times.

    Misconception

    "IR drop scales in proportion to the strap pitch."

    The rail drop between straps grows with the square of the spacing. Doubling the pitch can more than double that part.

    Source Lesson L3.5 key points

    • Lesson L3.5IR Drop and Electromigration
    • Problem L3.5.1Spend Fewer Straps on the Grid
11. Break ItWhat Well Taps Are ForL1 Junior

    What breaks if you forget the well-tap cells?

    Reveal the Model Answer

    The n-wells and p-substrate under the cells are no longer tied to their supplies, which invites latch-up. The sky130 high-density cells have no taps inside them, so tap cells must be placed in every row. Here they sit in a checkerboard about every 14 µm. The rule comes from the process; the lesson found no public numeric tap distance to check against.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 The n-wells and p-substrate under the cells are no longer tied to their supplies, which invites latch-up. Key point 2 The sky130 high-density cells have no taps inside them, so tap cells must be placed in every row. Key point 3 Here they sit in a checkerboard about every 14 µm. Key point 4 The rule comes from the process; the lesson found no public numeric tap distance to check against.

    • Lesson L3.4The Power Grid and Well Taps
    • Lesson L1.2Standard Cells: The Library's Building Blocks
    • Problem L3.4.1A Connected Grid with Floating Wells
12. Prove ItSolve L3.4.1: A Connected Grid with Floating WellsSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem L3.4.1