AHB Address and Data Phases

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItBreak ItCompareScale It

1. AHB Address and Data Phases
2. WhyWhat the AHB Pipeline BuysL1 Junior

   Why pipeline the address at all? What does the subordinate gain?

   Reveal the Model Answer

   It gains a full cycle between seeing the address and having to produce or take the data. That is time to decode and start a memory access. Meanwhile the bus still completes one transfer per cycle. Without the overlap, a bus must halve its throughput. Or it must force every subordinate to answer in the same cycle it sees the address.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 It gains a full cycle between seeing the address and having to produce or take the data. Key point 2 That is time to decode and start a memory access. Key point 3 Meanwhile the bus still completes one transfer per cycle. Key point 4 Without the overlap, a bus must halve its throughput. Key point 5 Or it must force every subordinate to answer in the same cycle it sees the address.

   What Interviewers Listen For (Junior)

   A good junior answer says the overlap keeps one transfer per cycle. It also gives the subordinate a full cycle to decode the address.

   • Lesson P4.1AHB in One Picture
   • Lesson P4.2Address Phase, Data Phase
3. What IfThe Two-Cycle AHB ERRORL1 JuniorL2 Mid-Level

   Why does an AHB ERROR response take two cycles when OKAY takes one?

   Reveal the Model Answer

   The bus is pipelined. When a subordinate starts an ERROR, the next transfer's address phase is already on the bus. The first cycle (HRESP high, HREADYOUT low) holds that address phase and warns the manager. In the second cycle (HRESP high, HREADYOUT high), the manager can drive IDLE. That cancels the next transfer before anyone takes it. Wait states before the error carry HRESP low.

   A token flies when an address phase is accepted. HRESP lit means ERROR.

   1. Cycle 1

      The store to 0x100 is accepted.

   2. Cycle 2

      0x100 completes with OKAY, and the store to 0x9000 is accepted at the same edge.

   3. Cycle 3

      First ERROR cycle: HRESP high, HREADY low. The store to 0x104 is already on the wires, but nothing is accepted at this edge.

   4. Cycle 4

      The manager has replaced it with IDLE. Second ERROR cycle: HREADY high, HRESP high. The 0x9000 store ends failed; the address phase taken here is IDLE.

   5. Cycle 5

      The bus is idle and OKAY again. 0x104 was never written: the dump reads 00 there.

   The first ERROR cycle is a wait state that exists to give the manager this one decision.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The bus is pipelined. Key point 2 When a subordinate starts an ERROR, the next transfer's address phase is already on the bus. Key point 3 The first cycle (HRESP high, HREADYOUT low) holds that address phase and warns the manager. Key point 4 In the second cycle (HRESP high, HREADYOUT high), the manager can drive IDLE. Key point 5 That cancels the next transfer before anyone takes it. Key point 6 Wait states before the error carry HRESP low.

   What Interviewers Listen For (Junior)

   A good junior answer gives the two ERROR cycles exactly. It links them to the next address already being on the bus.

   Spec Misquote

   After an ERROR the manager must abandon the rest of the burst.

   Cancelling is allowed, not required. Continuing the remaining beats is also acceptable. If the manager cancels, it drives IDLE during the two-cycle response.

   Source AMBA AHB Protocol Specification IHI 0033C §3.6.2 Early burst termination; §5.1.3 ERROR response

   Spec Misquote

   A one-cycle error is fine as long as HRESP is high when HREADYOUT is high.

   HRESP high with HREADYOUT high is only the second cycle. It must follow a first cycle with HREADYOUT low. A one-cycle error gives the manager no chance to cancel the next transfer.

   Source AMBA AHB Protocol Specification IHI 0033C §5.1 Subordinate transfer responses (Table 5-2); §5.1.3 ERROR response

   Misconception

   Read data that comes with ERROR is thrown away, so the subordinate can leave anything on HRDATA.

   The manager may still use read data that comes with an ERROR. So a subordinate cannot rely on ERROR to hide a value. Driving HRDATA to zero on a read error is recommended.

   Source AMBA AHB Protocol Specification IHI 0033C §5.1.3 ERROR response

   • Lesson P4.5The Two-Cycle ERROR
   • Lesson P4.10The AHB Checker
   • Problem P4.5.1A One-Cycle Error
   • Problem P4.10.1Properties for the AHB Link
4. What IfCancelling After an ERRORL2 Mid-Level

   Beat 2 of an INCR4 write gets ERROR, and the manager drives IDLE in the second error cycle. What happens to beat 3, and must the manager redo the burst later?

   Data phase         beat 1   beat 2   beat 2
   HRESP              OKAY     ERROR    ERROR
   HREADY             1        0        1
   Address HTRANS     SEQ      SEQ      IDLE
   What happens to the pipelined beat 3?

   Reveal the Model Answer

   Beat 3's address phase was on the bus during the first error cycle. The manager turns it into IDLE in the second cycle. So no subordinate ever takes it, because it is never accepted as NONSEQ or SEQ with HREADY high. The manager need not rebuild the remaining beats later. During that waited cycle, it may also change the address, which the normal hold rule forbids.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Beat 3's address phase was on the bus during the first error cycle. Key point 2 The manager turns it into IDLE in the second cycle. Key point 3 So no subordinate ever takes it, because it is never accepted as NONSEQ or SEQ with HREADY high. Key point 4 The manager need not rebuild the remaining beats later. Key point 5 During that waited cycle, it may also change the address, which the normal hold rule forbids.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer explains that the cancelled beat is never accepted by any subordinate. It also says the manager need not resend the rest of the burst.

   • Lesson P4.5The Two-Cycle ERROR
   • Lesson P4.11An AHB Agent: The Pipelined Driver and Monitor
   • Problem P4.5.1A One-Cycle Error
5. What IfA Manager That Continues After ERRORL2 Mid-Level

   What if the manager does not cancel, and drives beats 3 and 4 after the ERROR? Is that legal, and what should your checker accept?

   Reveal the Model Answer

   It is legal: cancelling the rest of the burst is allowed, not required. So the checker must accept both IDLE in the second error cycle and a burst that carries on. The subordinate answers the later beats normally. A checker that flags the continued burst reports a false failure on a legal manager.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 It is legal: cancelling the rest of the burst is allowed, not required. Key point 2 So the checker must accept both IDLE in the second error cycle and a burst that carries on. Key point 3 The subordinate answers the later beats normally. Key point 4 A checker that flags the continued burst reports a false failure on a legal manager.

   Spec Misquote

   "After an ERROR the manager must abandon the burst."

   The spec allows either choice. A checker built on that belief fails legal managers.

   Source AMBA AHB Protocol Specification IHI 0033C §3.6.2 Early burst termination

   Missed Corner

   "An ERROR on a read stops the manager using the data."

   The manager may still use it. That is why the spec recommends driving HRDATA to zero on an errored read.

   Source AMBA AHB Protocol Specification IHI 0033C §5.1.3 ERROR response

   • Lesson P4.5The Two-Cycle ERROR
   • Problem P4.5.1A One-Cycle Error
6. Break ItAsserting the Two-Cycle ERRORL2 Mid-Level

   A subordinate sometimes gives a one-cycle ERROR. Write assertions that catch it.

   Reveal the Model Answer

   Check both directions. A first ERROR cycle (HRESP high, HREADYOUT low) must be followed by a second (HRESP high, HREADYOUT high). And a second cycle must be preceded by a first. The one-cycle error passes the first property vacuously: there is no first cycle to trigger it. It fails only the second, so a checker with just one of them misses it.

   ap is 1 while a NONSEQ sits in the address phase. A token on the address wire is an address phase accepted at that edge.

   1. Cycle 1

      The write to 0x8000 is accepted at this edge: its data phase is the next cycle.

   2. Cycle 2

      The memory ends that data phase with HRESP and HREADY high together. The property err_first fails here: an ERROR must start with HREADY low. The same edge accepts the next address phase, the write to 0x600.

   3. Cycle 3

      The write to 0x600 completes with 77. A two-cycle ERROR would have given the manager the edge before this one to drive IDLE instead.

   Measured on the lesson bench. This ERROR has one cycle only, so the next write is accepted and completes.

   RUNVerilator · simulator service

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: t=65 second_needs_first failed t=90 done

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Check both directions. Key point 2 A first ERROR cycle (HRESP high, HREADYOUT low) must be followed by a second (HRESP high, HREADYOUT high). Key point 3 And a second cycle must be preceded by a first. Key point 4 The one-cycle error passes the first property vacuously: there is no first cycle to trigger it. Key point 5 It fails only the second, so a checker with just one of them misses it.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer writes both implications, first cycle to second and second cycle back to first. It explains why one of them alone misses the one-cycle error.

   • Lesson P4.10The AHB Checker
   • Lesson P4.5The Two-Cycle ERROR
   • Problem P4.10.1Properties for the AHB Link
7. CompareError Responses Across AMBAL2 Mid-LevelL3 Senior

   Compare AHB ERROR with APB PSLVERR and AXI SLVERR and DECERR. Where does an AHB decode error come from?

   Reveal the Model Answer

   AHB has one response bit, so a decode error is ERROR from the default subordinate for unmapped NONSEQ or SEQ transfers. APB's PSLVERR counts only in the single completion cycle, and needs no second cycle because APB is not pipelined. AXI separates SLVERR (the end point refused) from DECERR (no end point). It reports per read beat and once per write, and never shortens a burst. Bridges map PSLVERR to HRESP or to RRESP/BRESP.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 AHB has one response bit, so a decode error is ERROR from the default subordinate for unmapped NONSEQ or SEQ transfers. Key point 2 APB's PSLVERR counts only in the single completion cycle, and needs no second cycle because APB is not pipelined. Key point 3 AXI separates SLVERR (the end point refused) from DECERR (no end point). Key point 4 It reports per read beat and once per write, and never shortens a burst. Key point 5 Bridges map PSLVERR to HRESP or to RRESP/BRESP.

   What Interviewers Listen For (Mid-Level)

   A good mid-level answer gets the error signalling of AHB, APB and AXI right. It knows the default subordinate makes the decode error on AHB.

   • Lesson P4.5The Two-Cycle ERROR
   • Lesson P4.8Decoder, Multiplexor and the Default Subordinate
   • Lesson P3.4Errors: PSLVERR
   • Lesson P2.13Responses and Exclusive Access
   • Problem P4.8.2Decoder and Default Subordinate
8. Prove ItSolve P4.5.1: A One-Cycle ErrorSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem P4.5.1

9. What IfAHB Wait States, HREADY and HREADYOUTL1 JuniorL2 Mid-Level

   A subordinate inserts two wait states on a read. What happens on the bus during those cycles? And what is the difference between HREADY and HREADYOUT?

   Rising edge       0        1        2        3
   Address phase     READ A   next     held     held
   Data phase        prior    READ A   READ A   READ A
   HREADY            1        0        0        1
   HRDATA            -        ?        ?        D[A]
   Annotate the address/control signals that must remain stable.

   Reveal the Model Answer

   The wait states stretch the data phase of the read. They also stretch the address phase of the next transfer, which stays on the wires until HREADY is high. Each subordinate drives HREADYOUT for its own data phase. The multiplexor picks the HREADYOUT of the subordinate whose data phase is active. It sends that as HREADY to the manager and to every subordinate. A subordinate takes an address phase only at an edge where its HSEL and HREADY are both high.

   A token flies when an address phase is accepted: a transfer on HTRANS and HREADY high.

   1. Cycle 1

      A's address phase, 0x1000, is accepted: NONSEQ and HREADY high.

   2. Cycle 2

      A's data phase starts with 11 on HWDATA, and B's address 0x1010 is already on the wires. The memory drives HREADYOUT low: nothing is accepted at this edge.

   3. Cycle 3

      Still waiting. The manager holds both the data of A and the address of B exactly as they were.

   4. Cycle 4

      HREADY is high: A's data is written and B's address is accepted at the same edge.

   5. Cycle 5

      B's data, 22, moves while the read of 0x1000 is in its address phase. No waits this time.

   6. Cycle 6

      The read's data phase ends with 11 on HRDATA, the word A wrote.

   A wait state costs every transfer in the pipeline a cycle, not only the slow one.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 The wait states stretch the data phase of the read. Key point 2 They also stretch the address phase of the next transfer, which stays on the wires until HREADY is high. Key point 3 Each subordinate drives HREADYOUT for its own data phase. Key point 4 The multiplexor picks the HREADYOUT of the subordinate whose data phase is active. Key point 5 It sends that as HREADY to the manager and to every subordinate. Key point 6 A subordinate takes an address phase only at an edge where its HSEL and HREADY are both high.

   What Interviewers Listen For (Junior)

   A good junior answer says the next address phase is held during the wait. It tells HREADYOUT, one per subordinate, apart from HREADY, the shared bus signal.

   Missed Corner

   A monitor can count a transfer at every edge where HTRANS is NONSEQ or SEQ.

   While a data phase is stretched, the next transfer waits on the wires and shows NONSEQ at every edge. Below, the naive monitor logs 0x24 three times. Only edges with HREADY high count.

   Run It

   RUNIcarus Verilog · in your browser

   Edit the code, then run it

   OutputWaves

   RunReset codeExpected: t=15 naive monitor logs address 0x00000020 t=15 HREADY monitor logs address 0x00000020 t=25 naive monitor logs address 0x00000024 t=35 naive monitor logs address 0x00000024 t=45 naive monitor logs address 0x00000024 t=45 HREADY monitor logs address 0x00000024 FAIL naive monitor counted 4 address phases; the bus carried 2 PASS HREADY monitor counted 2 address phases; the bus carried 2

   Spec Misquote

   The manager may change the address freely during a wait state.

   It may change only while the waiting address phase is IDLE, or after an ERROR has started. Once it shows NONSEQ or SEQ, the address is held until HREADY is high.

   Source AMBA AHB Protocol Specification IHI 0033C §3.7.2 Address changes during wait states

   Misconception

   A subordinate only needs HSELx; HREADY is the manager's business.

   A selected subordinate must also see HREADY high. That tells it the previous transfer has finished, even if it belonged to another subordinate. Sampling on HSEL alone takes transfers that have not been accepted.

   Source AMBA AHB Protocol Specification IHI 0033C §2.4 Decoder signals; §4.2 Address decoding

   • Lesson P4.4Wait States and What May Change
   • Lesson P4.2Address Phase, Data Phase
   • Problem P4.4.1The Hold Checker
10. WhyWhy a Subordinate Takes HREADY InL1 JuniorL2 Mid-Level

    A subordinate drives HREADYOUT. Why does it also need the bus HREADY as an input?

    Reveal the Model Answer

    The data phase in front may belong to another subordinate. HREADY says when that data phase ends. Only then does the address phase on the wires count as accepted. A subordinate that samples on HSEL alone may act too early. The address phase may still change, such as an IDLE becoming NONSEQ, or the manager may cancel it after an ERROR.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 The data phase in front may belong to another subordinate. Key point 2 HREADY says when that data phase ends. Key point 3 Only then does the address phase on the wires count as accepted. Key point 4 A subordinate that samples on HSEL alone may act too early. Key point 5 The address phase may still change, such as an IDLE becoming NONSEQ, or the manager may cancel it after an ERROR.

    What Interviewers Listen For (Junior)

    A good junior answer says HREADY tells the subordinate that the transfer in front has finished.

    • Lesson P4.2Address Phase, Data Phase
    • Lesson P4.8Decoder, Multiplexor and the Default Subordinate
    • Problem P4.2.1A Zero-Wait AHB Subordinate
11. Break ItA Subordinate That Samples on HSEL AloneL2 Mid-Level

    Break it: a subordinate takes address and control whenever HSEL is high and ignores HREADY. Show the failure.

    Reveal the Model Answer

    While the data phase in front is in a wait state, HSEL and the address can already point at this subordinate. It then takes a transfer the bus has not accepted yet. If the manager changes IDLE to NONSEQ, or cancels after an ERROR, the subordinate acts on the wrong transfer. Across a long wait it can even take one transfer twice.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 While the data phase in front is in a wait state, HSEL and the address can already point at this subordinate. Key point 2 It then takes a transfer the bus has not accepted yet. Key point 3 If the manager changes IDLE to NONSEQ, or cancels after an ERROR, the subordinate acts on the wrong transfer. Key point 4 Across a long wait it can even take one transfer twice.

    Spec Misquote

    "HSEL is high, so the transfer is for me and I take it."

    HSEL only says the address decodes to you. The address phase counts only in a cycle where HREADY is high.

    Source AMBA AHB Protocol Specification IHI 0033C §4.2 Address decoding

    • Lesson P4.2Address Phase, Data Phase
    • Problem P4.2.1A Zero-Wait AHB Subordinate
12. What IfHTRANS During a Wait StateL2 Mid-Level

    While HREADY is low, may the manager change HTRANS? Give the exceptions.

    Reveal the Model Answer

    Normally no, with three exceptions. IDLE may become NONSEQ, and in a fixed-length burst BUSY may become SEQ. In an undefined-length INCR burst, BUSY may become anything, and IDLE or NONSEQ ends the burst. After any such change, HTRANS is held until HREADY is high. The address may change only for IDLE, or after an ERROR has started.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 Normally no, with three exceptions. Key point 2 IDLE may become NONSEQ, and in a fixed-length burst BUSY may become SEQ. Key point 3 In an undefined-length INCR burst, BUSY may become anything, and IDLE or NONSEQ ends the burst. Key point 4 After any such change, HTRANS is held until HREADY is high. Key point 5 The address may change only for IDLE, or after an ERROR has started.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer lists the three exceptions where HTRANS may change in a wait. It says HTRANS then holds until HREADY is high.

    • Lesson P4.4Wait States and What May Change
    • Lesson P4.10The AHB Checker
    • Problem P4.4.1The Hold Checker
    • Problem P4.10.1Properties for the AHB Link
13. Prove ItSolve P4.4.1: The Hold CheckerSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P4.4.1

14. Scale ItBounding AHB Wait StatesL3 Senior

    Why should every AHB subordinate have a known maximum number of wait states? How would you check that across an SoC?

    Reveal the Model Answer

    Wait states stall the whole AHB interface. So the worst-case latency of every manager depends on the slowest subordinate it can reach. A known maximum per subordinate lets you compute that latency. Check it with a watchdog per subordinate, set to its documented bound. Add performance tests that hit the worst case and, for small blocks, a bounded-response property in formal.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 Wait states stall the whole AHB interface. Key point 2 So the worst-case latency of every manager depends on the slowest subordinate it can reach. Key point 3 A known maximum per subordinate lets you compute that latency. Key point 4 Check it with a watchdog per subordinate, set to its documented bound. Key point 5 Add performance tests that hit the worst case and, for small blocks, a bounded-response property in formal.

    What Interviewers Listen For (Senior)

    A good senior answer explains that a wait state stalls the whole bus. It turns each subordinate's documented maximum wait into a checked parameter.

    • Lesson P4.4Wait States and What May Change
    • Lesson P4.10The AHB Checker
15. Break ItRules for an AHB MonitorL2 Mid-LevelL3 Senior

    Write down the rules your AHB monitor uses. When is an address phase taken, and when does its data phase end? What do monitors usually get wrong?

    Reveal the Model Answer

    An address phase is taken at an edge where HREADY is high and HTRANS is NONSEQ or SEQ. On a subordinate port, HSEL must be high too. Its data phase ends at the next edge where HREADY is high, and HWDATA, HRDATA and HRESP belong to it there. Monitors often log at the address phase and pair the wrong data. Others ignore HREADY and log a waiting transfer several times, or read HRESP as final in the first ERROR cycle.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 An address phase is taken at an edge where HREADY is high and HTRANS is NONSEQ or SEQ. Key point 2 On a subordinate port, HSEL must be high too. Key point 3 Its data phase ends at the next edge where HREADY is high, and HWDATA, HRDATA and HRESP belong to it there. Key point 4 Monitors often log at the address phase and pair the wrong data. Key point 5 Others ignore HREADY and log a waiting transfer several times, or read HRESP as final in the first ERROR cycle.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer names both edges correctly: where the address phase is taken and where its data phase ends. It keeps one pending transfer between them.

    • Lesson P4.11An AHB Agent: The Pipelined Driver and Monitor
    • Problem P4.11.1The AHB Monitor
16. Prove ItSolve P4.11.1: The AHB MonitorSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P4.11.1

17. Prove ItSolve P4.4.1: The Hold CheckerSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P4.4.1

18. CompareAHB Pipelining Against AXI Outstanding TransactionsL1 JuniorL2 Mid-Level

    Compare AHB's pipelining with AXI's outstanding transactions. When would you still pick AHB?

    Reveal the Model Answer

    AHB has one address and control path, with at most one transfer in address and one in data. Transfers complete in order, and a wait state stalls whatever is behind it. AXI has independent channels and IDs, so a manager can issue many requests without waiting. Responses with different IDs may return out of order. AHB wins on area and simplicity for a single manager with modest latency, such as a microcontroller memory bus.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 AHB has one address and control path, with at most one transfer in address and one in data. Key point 2 Transfers complete in order, and a wait state stalls whatever is behind it. Key point 3 AXI has independent channels and IDs, so a manager can issue many requests without waiting. Key point 4 Responses with different IDs may return out of order. Key point 5 AHB wins on area and simplicity for a single manager with modest latency, such as a microcontroller memory bus.

    What Interviewers Listen For (Junior)

    A good junior answer contrasts the two buses. AHB is two transfers deep and in order, while AXI allows many requests in flight, ordered by ID.

    • Lesson P4.1AHB in One Picture
    • Lesson P2.5Outstanding Transactions and Throughput
    • Lesson P2.10IDs and Same-ID Order: Why Responses Come Back in Order
19. Break ItRules for an AHB MonitorL2 Mid-LevelL3 Senior

    Write down the rules your AHB monitor uses. When is an address phase taken, and when does its data phase end? What do monitors usually get wrong?

    Reveal the Model Answer

    An address phase is taken at an edge where HREADY is high and HTRANS is NONSEQ or SEQ. On a subordinate port, HSEL must be high too. Its data phase ends at the next edge where HREADY is high, and HWDATA, HRDATA and HRESP belong to it there. Monitors often log at the address phase and pair the wrong data. Others ignore HREADY and log a waiting transfer several times, or read HRESP as final in the first ERROR cycle.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 An address phase is taken at an edge where HREADY is high and HTRANS is NONSEQ or SEQ. Key point 2 On a subordinate port, HSEL must be high too. Key point 3 Its data phase ends at the next edge where HREADY is high, and HWDATA, HRDATA and HRESP belong to it there. Key point 4 Monitors often log at the address phase and pair the wrong data. Key point 5 Others ignore HREADY and log a waiting transfer several times, or read HRESP as final in the first ERROR cycle.

    What Interviewers Listen For (Mid-Level)

    A good mid-level answer names both edges correctly: where the address phase is taken and where its data phase ends. It keeps one pending transfer between them.

    • Lesson P4.11An AHB Agent: The Pipelined Driver and Monitor
    • Problem P4.11.1The AHB Monitor
20. Prove ItSolve P4.11.1: The AHB MonitorSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P4.11.1

21. Prove ItSolve P4.2.1: A Zero-Wait AHB SubordinateSimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem P4.2.1