Where the Square Law Breaks Down

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItCompareScale It

1. Where the Square Law Breaks Down
2. WhyChecking the Square Law with a Square-Root PlotL1 JuniorL2 Mid-Level

   How can you tell from a simulation whether a device follows the square law?

   Reveal the Model Answer

   Plot the square root of the drain current against V_GS in saturation. A square-law device gives a straight line that crosses zero at the threshold. A bend at high V_GS shows mobility degradation and velocity saturation. The shape near the threshold shows the move into weak inversion.

   • s1
   • s2
   • s3
   • fit

   1. Gate-source voltage VGS 1 Vs1 = 11.91 · s2 = 12.31 · s3 = 14.92 · fit = 14.92

      s1, s2 and s3 are the 0.15, 0.3 and 1 µm devices. The fit passes through the long device here, at 14.92.

   2. Gate-source voltage VGS 1.2 Vs1 = 16.78 · s2 = 17.89 · s3 = 21.21 · fit = 21.21

      Second fit point: 21.21. The line's slope is 31.4 õA per volt, and it crosses zero at V_th = 0.526 V.

   3. Gate-source voltage VGS 1.5 Vs1 = 22.47 · s2 = 24.91 · s3 = 29.79 · fit = 30.64

      The long device already bends below its own line. The short one has bent from the start: its curve is flatter everywhere above 1 V.

   4. Gate-source voltage VGS 1.8 Vs1 = 27.04 · s2 = 30.64 · s3 = 37.36 · fit = 40.07

      The fit predicts 40.07, which is 1.606 mA. The long device reaches 37.36 (1.396 mA), 13 % short. The short one reaches 27.04 (0.731 mA), 54 % short.

   Read the plot as a table

   Gate-source voltage VGS	s1	s2	s3	fit
   0 V	0.001552	0.001454	0.001617	-16.53
   200 mV	0.00943	0.007676	0.01377	-10.24
   400 mV	0.1111	0.1006	0.1983	-3.949
   600 mV	1.146	1.086	2.037	2.34
   800 mV	5.787	5.911	8.148	8.629
   1 V	11.91	12.31	14.92	14.92
   1.2 V	16.78	17.89	21.21	21.21
   1.4 V	20.73	22.73	27.05	27.5
   1.5 V	22.47	24.91	29.79	30.64
   1.6 V	24.09	26.95	32.43	33.79
   1.8 V	27.04	30.64	37.36	40.07

   Measured on ngspice 42, SKY130 tt (901 points). The fit line is computed in the same run from the L = 1 µm curve.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Plot the square root of the drain current against V_GS in saturation. Key point 2 A square-law device gives a straight line that crosses zero at the threshold. Key point 3 A bend at high V_GS shows mobility degradation and velocity saturation. Key point 4 The shape near the threshold shows the move into weak inversion.

   • Lesson E2.3The Square Law and Where SKY130 Departs from It
   • Problem E2.1.1A Switching Point at Mid-Rail
3. Prove ItSolve E2.1.1: A Switching Point at Mid-RailSimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem E2.1.1

4. CompareSizing a Transistor with gm/IDL1 JuniorL2 Mid-Level

   You need g_m = 200 µS from an NMOS at a chosen length. Describe, step by step, how you size it with the g_m/I_D method (g_m/I_D is transconductance per unit of drain current).

   Reveal the Model Answer

   Pick g_m/I_D for the trade you want: high for low current, low for speed. Then I_D is g_m divided by g_m/I_D. Read the current density I_D/W from a measured chart for that length, and get W as I_D over that density. Finally check g_m on a bench. The chart works in any inversion region, where the square law would not.

   • L = 0.15 µm
   • L = 0.5 µm
   • L = 1 µm

   1. log10 of I_D/W (A per µm) -10.5L = 0.15 µm = 25.18 · L = 0.5 µm = 26.45 · L = 1 µm = 28.31

      At 32 pA/µm every length is deep in weak inversion, flat at its limit 1/(n·U_T): 25.2, 26.4 and 28.3 per volt.

   2. log10 of I_D/W (A per µm) -6.198L = 0.15 µm = 21.16 · L = 0.5 µm = 20 · L = 1 µm = 18.16

      The L = 0.5 µm curve crosses 20 at 0.634 µA/µm; above 20 we call a device weakly inverted.

   3. log10 of I_D/W (A per µm) -6L = 0.15 µm = 20.3 · L = 0.5 µm = 18.78 · L = 1 µm = 16.5

      At 1 µA/µm the lengths spread to 20.3, 18.8 and 16.5, because a longer device leaves weak inversion at a lower density.

   4. log10 of I_D/W (A per µm) -5.557L = 0.15 µm = 17.83 · L = 0.5 µm = 15 · L = 1 µm = 12.07

      L = 0.5 µm reaches 15 at 2.77 µA/µm, in the middle of moderate inversion, where the sizing example below starts.

   5. log10 of I_D/W (A per µm) -5L = 0.15 µm = 13.61 · L = 0.5 µm = 9.168 · L = 1 µm = 6.647

      At 10 µA/µm the values are 13.6, 9.17 and 6.65, and the long devices are now in strong inversion, below 10.

   6. log10 of I_D/W (A per µm) -4L = 0.15 µm = 4.114 · L = 0.5 µm = 2.295 · L = 1 µm = 1.427

      At 100 µA/µm g_m/I_D has fallen to 4.11, 2.29 and 1.43, so pushing more current through the same width buys little extra g_m.

   Read the plot as a table

   log10 of I_D/W (A per µm)	L = 0.15 µm	L = 0.5 µm	L = 1 µm
   -10.5	25.18	26.45	28.31
   -10	25.16	26.35	28.15
   -9	25.04	25.89	27.4
   -8	24.65	24.7	25.54
   -7	23.47	22.67	22.44
   -6.198	21.16	20	18.16
   -6	20.3	18.78	16.5
   -5.557	17.83	15	12.07
   -5	13.61	9.168	6.647
   -4	4.114	2.295	1.427

   The measured chart this method reads: g_m/I_D against current density, one curve per length.

   1. The current is set

      IB pushes 6.667 µA into the drain, and M3 must carry all of it.

      6.667 µA

   2. The amplifier finds the gate voltage

      If the drain rises above 0.9 V, the amplifier raises the gate, M3 conducts more and pulls the drain back down, until the loop settles with V_GS = 0.715 V.

   3. Read gm

      Sweep IB a little and watch the gate: g_m = ΔI_D/ΔV_GS, and the lab measures 100.3 µS.

   Read the circuit as text

   • IB current source (6.667 µA): + → VDD, − → d3
   • M3 NMOS transistor (W/L = 2.4/0.5): gate → g3, drain → d3, source → 0
   • E1 op-amp: −in → n1, +in → d3, out → g3
   • VREF voltage source (0.9 V): + → n1, − → 0

   • d3 = 0.900 V
   • g3 = 0.715 V

   The last step: a bench that holds the sized device at its bias and measures g_m.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Pick g_m/I_D for the trade you want: high for low current, low for speed. Key point 2 Then I_D is g_m divided by g_m/I_D. Key point 3 Read the current density I_D/W from a measured chart for that length, and get W as I_D over that density. Key point 4 Finally check g_m on a bench. Key point 5 The chart works in any inversion region, where the square law would not.

   What Interviewers Listen For (Junior)

   A good junior answer walks through the four steps in order. It explains what a high g_m/I_D costs and what a low one costs.

   Misconception

   "g_m/I_D = 2/V_ov, so a small overdrive gives unlimited efficiency."

   That is the square law. The device saturates at about 1/(n·U_T), 25 to 28 V⁻¹ for the sky130 1.8 V NMOS, once it enters weak inversion.

   Source ASIC Point lesson E2.5 (measured; Jespers and Murmann, as cited)

   Half-Truth

   "Always bias at the highest g_m/I_D to save power."

   High g_m/I_D needs wide devices with large capacitance, so the transistor gets slow. The choice is a trade between current, area and speed.

   • Lesson E2.5Transconductance and gm/ID
   • Lesson E5.7Capstone: A Five-Transistor OTA to Spec
   • Problem E5.3.1A Bench for the Five-Transistor OTA
5. WhyWhy One Chart per Length Is EnoughL2 Mid-Level

   Why does one measured g_m/I_D chart per channel length size a device of any width?

   Reveal the Model Answer

   At a fixed length, g_m/I_D depends on how hard the channel is driven. The current density I_D/W captures that, not the width itself. Doubling W at the same density doubles I_D and g_m and leaves g_m/I_D unchanged. So one curve of g_m/I_D against density per length covers every width.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 At a fixed length, g_m/I_D depends on how hard the channel is driven. Key point 2 The current density I_D/W captures that, not the width itself. Key point 3 Doubling W at the same density doubles I_D and g_m and leaves g_m/I_D unchanged. Key point 4 So one curve of g_m/I_D against density per length covers every width.

   • Lesson E2.5Transconductance and gm/ID
6. Prove ItSolve E5.3.1: A Bench for the Five-Transistor OTASimulator-graded

   Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

   Open Problem E5.3.1

7. What IfChanging Length After Sizing from the ChartL2 Mid-Level

   What if you change the channel length after sizing from the chart? Can you keep the same chart?

   Reveal the Model Answer

   No. The chart holds for one length, because g_m/I_D at a given density changes with L. Take the chart for the new length and read a new density for the same g_m/I_D. A longer device gives more r_o and gain, but it adds capacitance and is slower.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 No. Key point 2 The chart holds for one length, because g_m/I_D at a given density changes with L. Key point 3 Take the chart for the new length and read a new density for the same g_m/I_D. Key point 4 A longer device gives more r_o and gain, but it adds capacitance and is slower.

   Misconception

   "Keep W/L the same and the operating point does not change."

   That holds only under the square law. Short-channel effects change g_m/I_D at a fixed W/L, so read the chart for the new length.

   Source Lesson E2.5 key points

   • Lesson E2.5Transconductance and gm/ID
   • Lesson E2.4Channel-Length Modulation and Output Resistance
   • Problem E5.3.1A Bench for the Five-Transistor OTA
8. CompareHigh vs Low gm/IDL1 JuniorL2 Mid-Level

   Compare biasing a transistor at high g_m/I_D with biasing it at low g_m/I_D.

   Reveal the Model Answer

   High g_m/I_D, near weak inversion, gives the most transconductance per microamp. But the device is wide and slow, and its threshold mismatch becomes a larger current error. Low g_m/I_D, strong inversion, costs current but gives small, fast devices and better current matching. Input pairs often sit high for noise and offset; mirrors and fast stages sit lower.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 High g_m/I_D, near weak inversion, gives the most transconductance per microamp. Key point 2 But the device is wide and slow, and its threshold mismatch becomes a larger current error. Key point 3 Low g_m/I_D, strong inversion, costs current but gives small, fast devices and better current matching. Key point 4 Input pairs often sit high for noise and offset; mirrors and fast stages sit lower.

   • Lesson E2.5Transconductance and gm/ID
   • Lesson E7.4Mismatch and Pelgrom's Law
9. Scale ItDesigning an OTA to a SpecificationL2 Mid-LevelL3 Senior

   You get a brief for an OTA: load, unity-gain frequency, current budget, gain and input range. In what order do you size it?

   Reveal the Model Answer

   Start with f_u and C_L, which give g_m. The current budget then gives g_m/I_D (transconductance per unit current), and a measured chart gives W. The gain sets the length, and the input range checks the tail and the load. Keep margin on f_u, because the output node carries more than C_L. Check every line at every input level the brief names.

   1. Speed sets gm

      Into a capacitive load, f_u = g_m1/(2πC_L), so g_m1 ≥ 2π × 10 MHz × 2 pF = 125.7 µS. The output node carries more than C_L, and the low end of the input range costs current, so aim 25 % higher: 157 µS.

   2. Current sets gm/ID

      Keep 2 µA for the bias diode and copy it eight times for a 16 µA tail: about 8 µA per input device. Then g_m/I_D ≥ 157/8 = 19.6 V⁻¹. Pick 22, in moderate inversion.

   3. The chart sets W; gain sets L

      The chart below gives 0.181 µA/µm at g_m/I_D = 22, so W = 8 µA / 0.181 µA/µm = 44 µm: take 40. Gain is g_m/(g_ds2 + g_ds4); at a fixed current only L moves the g_ds terms, and L = 1 µm clears 40 dB in E5.3's OTA.

   4. Range, then simulate

      The lower edge is V_GS1 + V_Dsat5: a wide pair keeps V_GS1 low and a wide tail (8 × 8/2) keeps V_Dsat5 low. The upper edge is VDD − V_SG3 + V_th1: a 4/1 load keeps V_SG3 small. Then run every line of the brief.

   Read the diagram as text

   • fu and CL: 10 MHz into 2 pF
   • gm of M1 and M2: ≥ 125.7 µS; aim 157 µS
   • Current budget: 2 µA bias + 16 µA tail
   • gm/ID: ≥ 19.6 /V; pick 22
   • Width from chart: 0.181 µA/µm: W = 40 µm
   • Length for gain: L = 1 µm for M1-M4
   • Input range: tail 8 × 8/2, load 4/1
   • Simulate and compare: every line at 0.7, 0.9, 1.1 V

   • fu and CL → gm of M1 and M2: 2π·fu·CL
   • gm of M1 and M2 → gm/ID
   • Current budget → gm/ID: I_D ≈ 8 µA
   • gm/ID → Width from chart
   • Width from chart → Length for gain
   • Length for gain → Input range
   • Input range → Simulate and compare

   Hand numbers come from formulas; the chart and the check come from runs.

   Self-Check

   Tick each key point you covered in your answer.

   Key point 1 Start with f_u and C_L, which give g_m. Key point 2 The current budget then gives g_m/I_D (transconductance per unit current), and a measured chart gives W. Key point 3 The gain sets the length, and the input range checks the tail and the load. Key point 4 Keep margin on f_u, because the output node carries more than C_L. Key point 5 Check every line at every input level the brief names.

   • Lesson E5.7Capstone: A Five-Transistor OTA to Spec
   • Problem E5.3.1A Bench for the Five-Transistor OTA
10. Prove ItSolve E5.3.1: A Bench for the Five-Transistor OTASimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem E5.3.1

11. Prove ItSolve E5.3.1: A Bench for the Five-Transistor OTASimulator-graded

    Show it, don't just say it: this Silicon Lab problem is graded by the simulator.

    Open Problem E5.3.1

12. Scale ItProcess Corners and Temperature for One DeviceL2 Mid-LevelL3 Senior

    How much does a sky130 device move across process corners and temperature, and what does that mean for sign-off?

    Reveal the Model Answer

    A lot: the short NMOS current moved from -29 % to +38 % and the short PMOS from -47 % to +68 % across the corners. Heat lowers both threshold and mobility, so below the zero-temperature-coefficient bias the current rises with temperature and above it falls. Sign-off crosses corners with the supply range and both temperature ends. Check each corner's name by measurement: here sf is fast NMOS, slow PMOS, the opposite of the library comment.

    Self-Check

    Tick each key point you covered in your answer.

    Key point 1 A lot: the short NMOS current moved from -29 % to +38 % and the short PMOS from -47 % to +68 % across the corners. Key point 2 Heat lowers both threshold and mobility, so below the zero-temperature-coefficient bias the current rises with temperature and above it falls. Key point 3 Sign-off crosses corners with the supply range and both temperature ends. Key point 4 Check each corner's name by measurement: here sf is fast NMOS, slow PMOS, the opposite of the library comment.

    • Lesson E2.7Corners and Temperature
    • Lesson E7.6Corners and PVT Sign-Off
    • Problem E2.7.1The Same Current at Every Corner