Interview Question · Concept

Subthreshold Swing and Leakage

L1 JuniorL2 Mid-Levelmosleakage

The interviewer asks

What sets how fast a transistor turns off below threshold, and how would you measure its off current in SPICE?

Reveal the Model Answer

Below threshold the current is diffusion over a barrier, so it is exponential in V_GS. The subthreshold swing, n·U_T·ln 10, is the gate voltage per decade of current. It is 59.6 mV at best at 27 °C and about 94 mV for this sky130 NMOS. The off current is the current at V_GS = 0; it grows with temperature and drain voltage. In SPICE, lower gmin first, because its default conductance adds about 1.8 pA at 1.8 V.

DC sweepDrain Current on a Log Axis at 27 °C and 125 °CNMOS W = 2 µm, L = 0.15 µm, V_DS = 1.8 V, gmin lowered to 10⁻¹⁸ S. Each grid line up is ten times more current.

I_D at 27 °C
I_D at 125 °C

Gate voltage V_GS 0 VI_D at 27 °C = 1.02 pA · I_D at 125 °C = 152.7 pA
With the gate at 0 V the device is off, yet 1.02 pA flows at 27 °C and 152.7 pA at 125 °C. This is the off current I_off.
Gate voltage V_GS 280 mVI_D at 27 °C = 1.004 nA · I_D at 125 °C = 27.04 nA
At 0.28 V the 27 °C curve passes 1 nA. Below about 0.5 V it is a straight line on this log axis: the current is exponential in V_GS.
Gate voltage V_GS 374 mVI_D at 27 °C = 10.05 nA · I_D at 125 °C = 148.3 nA
At 0.374 V it passes 10 nA. One decade of current took 94 mV of gate voltage.
Gate voltage V_GS 600 mVI_D at 27 °C = 1.929 µA · I_D at 125 °C = 6.201 µA
At 0.6 V the lines bend over as the channel forms. The hot device still leads, by 3.2 times.
Gate voltage V_GS 1 VI_D at 27 °C = 197.9 µA · I_D at 125 °C = 195.5 µA
At 1 V the curves meet: 197.9 µA at 27 °C and 195.5 µA at 125 °C. With a strong gate drive, heat no longer helps (E2.7).

Read the plot as a table

Gate voltage V_GS	I_D at 27 °C	I_D at 125 °C
0 V	1.02 pA	152.7 pA
200 mV	140.1 pA	6.217 nA
280 mV	1.004 nA	27.04 nA
374 mV	10.05 nA	148.3 nA
400 mV	18.92 nA	235.5 nA
600 mV	1.929 µA	6.201 µA
800 mV	47.97 µA	60.58 µA
1 V	197.9 µA	195.5 µA

Measured on a short sky130 NMOS. Below threshold the curve is a straight line on the log axis: one decade per swing.

DC sweepThe Same Device at −40 °C with Two Values of GminNMOS W = 2 µm, L = 0.15 µm, V_DS = 1.8 V. Only the gmin option differs between the runs.

gmin = 1e-18 S
gmin = 1e-12 S (default)

Gate voltage V_GS 0 Vgmin = 1e-18 S = 12.84 fA · gmin = 1e-12 S (default) = 1.813 pA
At V_GS = 0 the default run reports 1.81 pA. The device itself carries 0.0128 pA, 141 times less.
Gate voltage V_GS 200 mVgmin = 1e-18 S = 1.641 pA · gmin = 1e-12 S (default) = 3.441 pA
At 0.2 V the two runs still differ by a factor of two: 3.44 pA against 1.64 pA.
Gate voltage V_GS 300 mVgmin = 1e-18 S = 39.03 pA · gmin = 1e-12 S (default) = 40.83 pA
By 0.3 V the device current, 39 pA, swamps the 1.8 pA and the curves join.

Read the plot as a table

Gate voltage V_GS	gmin = 1e-18 S	gmin = 1e-12 S (default)
0 V	12.84 fA	1.813 pA
100 mV	78.08 fA	1.878 pA
200 mV	1.641 pA	3.441 pA
300 mV	39.03 pA	40.83 pA
400 mV	927.9 pA	929.7 pA
500 mV	21.42 nA	21.42 nA
600 mV	433.7 nA	433.7 nA

The same device with the default and a lowered gmin. At V_GS = 0, the default gmin adds more current than the device carries.

Self-Check

Tick each key point you covered in your answer.

Key point 1 Below threshold the current is diffusion over a barrier, so it is exponential in V_GS. Key point 2 The subthreshold swing, n·U_T·ln 10, is the gate voltage per decade of current. Key point 3 It is 59.6 mV at best at 27 °C and about 94 mV for this sky130 NMOS. Key point 4 The off current is the current at V_GS = 0; it grows with temperature and drain voltage. Key point 5 In SPICE, lower gmin first, because its default conductance adds about 1.8 pA at 1.8 V.

What Interviewers Listen For (Junior)

A good junior answer defines the swing and gives the limit of about 60 mV per decade. It measures the current at V_GS = 0.

Cross-Questions

Where the interviewer goes next. Open a node to practise that follow-up.

WhyWhat IfProve ItCompareScale It

Subthreshold Swing and Leakage
WhyWhy the Swing Cannot Beat 60 mV per DecadeL2 Mid-Level
Why can a MOSFET at room temperature not turn off faster than about 60 mV per decade?

Reveal the Model Answer

Below threshold carriers cross the source barrier by thermal diffusion, so the current follows the Boltzmann factor, exp(qV/kT). The gate controls the barrier only through a capacitive divider, which the slope factor n ≥ 1 describes. One decade therefore needs at least ln 10 · kT/q, about 59.6 mV at 27 °C, and more by the factor n.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Below threshold carriers cross the source barrier by thermal diffusion, so the current follows the Boltzmann factor, exp(qV/kT). Key point 2 The gate controls the barrier only through a capacitive divider, which the slope factor n ≥ 1 describes. Key point 3 One decade therefore needs at least ln 10 · kT/q, about 59.6 mV at 27 °C, and more by the factor n.
- Lesson E2.6Subthreshold and Leakage
Prove ItSolve E2.6.1: A Bench for the Sleep SwitchSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem E2.6.1
CompareLeakage vs Temperature and Drain VoltageL1 JuniorL2 Mid-Level
Compare how temperature and drain voltage change a device's off current.

Reveal the Model Answer

Temperature raises it by orders of magnitude, because the threshold falls and the swing widens. On this device the swing goes from 73 to 125 mV per decade between -40 °C and 125 °C. Drain voltage raises it through barrier lowering, about tenfold from 0.1 V to 1.8 V here. Standby power is therefore quoted at the hot corner and full supply.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Temperature raises it by orders of magnitude, because the threshold falls and the swing widens. Key point 2 On this device the swing goes from 73 to 125 mV per decade between -40 °C and 125 °C. Key point 3 Drain voltage raises it through barrier lowering, about tenfold from 0.1 V to 1.8 V here. Key point 4 Standby power is therefore quoted at the hot corner and full supply.
- Lesson E2.6Subthreshold and Leakage

Scale ItReviewing an Analog Block Before Tape-OutL3 SeniorL4 Staff

Asked if they ask how leakage is signed off

You review a colleague's op-amp and bias block a month before tape-out. What evidence do you ask for before you accept it?

Reveal the Model Answer

Ask for every specification line with its measured margin at every corner, crossed with supply and temperature. Ask for Monte Carlo mean plus or minus 3σ on offset and matching. Check stability at the worst load and feedback factor, with a step as well as a margin. Check start-up with supply ramps, fast and cold-slow. Finally, ask which known faults the benches were shown to catch.

One Bench Against Five BuffersArrows carry the same stimulus to each copy and the measured lines back to the verdict.

Dynamic faults
No R_z and a starved bias leave the settled DC levels right, so only the settling lines catch them for sure.

Read the diagram as text

Your bench: stimulus and meas lines
Final design
No Rz: phase margin
Bias 5 µA: slew rate
Load mirror 4/2: input range
M2 22/2: offset
Verdicts: pass, fail × 4

Your bench → Final design
Your bench → No Rz
Your bench → Bias 5 µA
Your bench → Load mirror 4/2
Your bench → M2 22/2
Final design → Verdicts
No Rz → Verdicts
Bias 5 µA → Verdicts
Load mirror 4/2 → Verdicts
M2 22/2 → Verdicts

AC analysisLoop Gain of OPA-B in the Sf Corner, Nominal and Cold at Low SupplyThe same op-amp, the same corner. Only the supply (1.8 → 1.62 V) and the temperature (27 → −40 °C) change.

sf, 1.8 V, 27 °C
sf, 1.62 V, −40 °C

Read the plot as a table

Frequency	sf, 1.8 V, 27 °C	sf, 1.62 V, −40 °C
1 Hz	79.77 dB	60.13 dB
10 Hz	79.77 dB	60.13 dB
100 Hz	79.76 dB	60.13 dB
1 kHz	79.17 dB	60.12 dB
10 kHz	67.83 dB	59.42 dB
100 kHz	48.11 dB	47.38 dB
1 MHz	28.11 dB	27.61 dB
10 MHz	7.725 dB	7.411 dB
100 MHz	-18.93 dB	-17 dB
1 GHz	-49.24 dB	-45.32 dB

One corner, two conditions. Only the supply and the temperature change, and the loop gain changes with them.

Self-Check

Tick each key point you covered in your answer.

Key point 1 Ask for every specification line with its measured margin at every corner, crossed with supply and temperature. Key point 2 Ask for Monte Carlo mean plus or minus 3σ on offset and matching. Key point 3 Check stability at the worst load and feedback factor, with a step as well as a margin. Key point 4 Check start-up with supply ramps, fast and cold-slow. Key point 5 Finally, ask which known faults the benches were shown to catch.

What Interviewers Listen For (Senior)

A good senior answer asks for PVT corners crossed with Monte Carlo, and for stability in the worst case. It also asks for start-up transients and proof that the benches work.

Missed Corner

"It meets spec at typical with an ideal bias source."

An ideal bias source hides the biggest process effect. The real reference current moves with process, supply and temperature, so the corners must use it.

Source ASIC Point lesson E7.6

Half-Truth

"All the DC checks pass, so the benches are good."

DC-level checks never see a missing R_z or a starved bias. A bench is trusted only after it fails known faults.

Source ASIC Point lesson E8.4

Wrong Altitude

Reviews only the schematic numbers.

Layout adds gradients and parasitics, and system use adds loads and supply noise. A senior review asks how those were covered.

WhyWhy a Bench Must Fail Known FaultsL2 Mid-LevelL3 Senior

Why should a test bench be shown to fail on purpose before you trust it?

Reveal the Model Answer

A bench that passes everything may not be measuring what you think. Insert known faults, such as a missing R_z, a starved bias or a swapped input. A good bench fails each one with a clear reason. In the lesson, DC-level checks missed both a missing R_z and a starved bias.

TransientThe Final Design and the Two Dynamic Faults

final design
no R_z
bias 5 µA

Time 370 nsfinal design = 61.54 µV · no R_z = 17.13 mV · bias 5 µA = 164.3 mV
70 ns after the fall only the final design has settled for good. Without R_z the output rings until 112.3 ns; the starved copy slews until 176.1 ns.

Read the plot as a table

Time	final design	no R_z	bias 5 µA
0 s	50.28 µV	50.28 µV	93.29 µV
100 ns	50.28 µV	50.28 µV	93.29 µV
200 ns	215.5 µV	-3.915 mV	-29.01 mV
300 ns	789.4 µV	819.1 µV	-6.087 mV
370 ns	61.54 µV	17.13 mV	164.3 mV
400 ns	51.91 µV	2.84 mV	34.21 mV
500 ns	-1.362 mV	-1.29 mV	5.276 mV
600 ns	96.08 µV	-1.484 mV	22.49 mV
700 ns	75.11 µV	110.3 µV	902.4 µV
800 ns	96.97 µV	155.3 µV	108.6 µV
900 ns	96.97 µV	96.41 µV	129.2 µV

Measured on ngspice 42; clipped at ±20 mV.

Self-Check

Tick each key point you covered in your answer.

Key point 1 A bench that passes everything may not be measuring what you think. Key point 2 Insert known faults, such as a missing R_z, a starved bias or a swapped input. Key point 3 A good bench fails each one with a clear reason. Key point 4 In the lesson, DC-level checks missed both a missing R_z and a starved bias.

Prove ItSolve E8.4.1: Break the DAC BufferSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem E8.4.1
What IfChoosing the Faults to Plant in a BenchL2 Mid-LevelL3 Senior
Which faults would you plant in a DAC output buffer bench, and which check should catch each one?

Reveal the Model Answer

Plant faults that a weak bench would miss. Remove R_z: the step settling check at speed must show ringing. Starve the bias: the input-range check at speed must fail near the top code. Swap the inputs: the open-loop sign check must fail. Each check that never fails is measuring nothing useful.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Plant faults that a weak bench would miss. Key point 2 Remove R_z: the step settling check at speed must show ringing. Key point 3 Starve the bias: the input-range check at speed must fail near the top code. Key point 4 Swap the inputs: the open-loop sign check must fail. Key point 5 Each check that never fails is measuring nothing useful.

Tool as Truth

"The DC sweeps pass with every fault, so the faults are harmless."

DC checks cannot see stability or slew. In the lesson they missed both a missing R_z and a starved bias.

Source Lesson E8.4 key points
CompareProcess Corners vs Monte CarloL1 JuniorL2 Mid-Level
Compare process corners with a mismatch Monte Carlo run. Do you need both?

Reveal the Model Answer

Yes. A process corner moves every transistor of a type together, the global spread between wafers. Mismatch moves each transistor alone, the local spread on one die. Offset comes mostly from mismatch, while bias currents and speed move mostly with corners. Sign-off runs corners crossed with supply and temperature, plus Monte Carlo.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Yes. Key point 2 A process corner moves every transistor of a type together, the global spread between wafers. Key point 3 Mismatch moves each transistor alone, the local spread on one die. Key point 4 Offset comes mostly from mismatch, while bias currents and speed move mostly with corners. Key point 5 Sign-off runs corners crossed with supply and temperature, plus Monte Carlo.
Prove ItSolve E7.6.1: Nine Settings, One VerdictSimulator-graded

Show it, don't just say it: this Silicon Lab problem is graded by the simulator.
Open Problem E7.6.1
Scale ItWriting a Bias Block SpecificationL3 Senior
You must hand over a bias block to other designers. How do you write its specification and prove it?
2:30

You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.

Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
Reveal the Model Answer

Write each requirement as one line with a limit and a measurement, set after measuring a reference design at every corner. Use one bench per check. Run a supply sweep and a temperature and supply sweep for the worst case. Add an output sweep for compliance and power-up transients, fast and slow. A constant-g_m reference moves its current on purpose, so specify the tail current as a band.

The Bias Block, Piece by PieceArrows show where a current or a gate voltage goes. W/L in µm.

Reference and start-up
The beta multiplier of E4.4 sets 10 µA with a res_high_po resistor (W = 0.35 µm, L = 8.54 µm). The start-up of E4.5 kicks it on at power-up and then switches off.
Send currents
PMOS devices on the reference's gate line b copy its current: 10 µA for the NMOS reference stack and 2.5 µA for the cascode bias. Currents travel; gate voltages stay local (E4.2).
Wide-swing cascode
The 2.5 µA diode XBC sets the cascode gate c. The reference stack sets the bottom gate g with its own cascode, so both bottom devices see the same drain voltage (E4.3). The tail is two units of the stack: 20 µA.
PMOS bias output
One more unit on gate g sinks 10 µA from a diode-connected 8/1 PMOS. Its gate is pbias: any 8/1 PMOS with its source at VDD and this gate voltage sources about 10 µA.

Read the diagram as text
Start-up: XS1-XS3: kick at power-up, then off
Reference: Beta multiplier, K = 4, RS a res_high_po: 10 µA
PMOS copies: XP3 4/1: 10 µA; XP4 1/1: 2.5 µA
Cascode bias: XBC 0.5/1.5 diode sets node c
Reference stack: XC1 over XB1, 16/1 units: node g
Tail output: XC2 over XB2, two units: 20 µA
PMOS bias output: XB3 sinks 10 µA from XPB 8/1
Start-up → Reference: kick
Reference → PMOS copies: gate b
PMOS copies → Cascode bias: 2.5 µA
PMOS copies → Reference stack: 10 µA
Cascode bias → Tail output: gate c
Reference stack → Tail output: gate g
Reference stack → PMOS bias output: gate g

The full netlist is the Try it below. Units are whole devices (m=2 for the tail), so the 2:1 ratio does not depend on drawn widths matching.

Self-Check
Tick each key point you covered in your answer.
Key point 1 Write each requirement as one line with a limit and a measurement, set after measuring a reference design at every corner. Key point 2 Use one bench per check. Key point 3 Run a supply sweep and a temperature and supply sweep for the worst case. Key point 4 Add an output sweep for compliance and power-up transients, fast and slow. Key point 5 A constant-g_m reference moves its current on purpose, so specify the tail current as a band.
- Lesson E4.7Capstone: A Bias Block to Spec
- Problem E4.7.1Catch the Bad Bias Block
What IfA DAC Buffer's Input Range at the CornersL2 Mid-LevelL3 Senior
Asked if the block drives a DAC or ADC

What if a DAC output buffer passes at typical but a corner moves its input range?
2:30

You have two and a half minutes. Speak or type, then press Get Feedback under your answer. No credits needed.

Speech-to-text runs in your browser. Chrome and Edge may send audio to their own speech service.
Reveal the Model Answer

A corner can push an edge of the input range past the top or bottom code. Then the buffer's tail leaves saturation at that code and the output error jumps. Choose the DAC references inside the buffer's range at speed, not just where the DC error is small. Check them at every corner.

DC sweepDC Error at Sf, −40 °C: Versions 2 and 3

version 2
version 3

Read the plot as a table
Input version 2 version 3
700 mV -149.8 µV -88.19 µV
800 mV 13.66 µV 37.73 µV
900 mV 48.87 µV 64.35 µV
1 V 93.74 µV 89.88 µV
1.1 V 630.6 µV 211.5 µV
1.2 V 10.28 mV 2.951 mV
1.3 V 47.59 mV 33.11 mV

DC error at the sf corner and -40 °C. At the top code, version 2 errs by 9.02 mV and version 3 by 2.42 mV.

Self-Check
Tick each key point you covered in your answer.
Key point 1 A corner can push an edge of the input range past the top or bottom code. Key point 2 Then the buffer's tail leaves saturation at that code and the output error jumps. Key point 3 Choose the DAC references inside the buffer's range at speed, not just where the DC error is small. Key point 4 Check them at every corner.

Input	version 2	version 3
700 mV	-149.8 µV	-88.19 µV
800 mV	13.66 µV	37.73 µV
900 mV	48.87 µV	64.35 µV
1 V	93.74 µV	89.88 µV
1.1 V	630.6 µV	211.5 µV
1.2 V	10.28 mV	2.951 mV
1.3 V	47.59 mV	33.11 mV

What People Get Wrong

Common wrong answers and why they fail. Run It shows the wrong belief failing on a real simulator.

Tool as Truth

"The off current SPICE prints is the device leakage."

With the default gmin the simulator's own conductance adds about 1.8 pA, so this device reads 2.82 pA at 27 °C and 1.81 pA at -40 °C. With gmin lowered it is 1.02 pA and 0.0128 pA.

Run It

The off-current bench from lesson E2.6 with the default gmin.

SPICEngspice 42 · simulator service

Edit the netlist, then run it

Expected: ioff_27 = 2.819966e-12 ioff_m40 = 1.812835e-12

* off current and subthreshold swing of an NMOS (W = 2, L = 0.15)
.lib sky130 tt
XM1 d g 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15
VDS d 0 1.8
VGS g 0 0
.control
* 27 C, VDS = 1.8 V
dc VGS 0 0.6 0.002
let id = -i(VDS)
meas dc ioff_27 FIND id AT=0
meas dc s_27 TRIG id VAL=1n RISE=1 TARG id VAL=10n RISE=1
* 125 C
option temp=125
dc VGS 0 0.6 0.002
let id = -i(VDS)
meas dc ioff_125 FIND id AT=0
meas dc s_125 TRIG id VAL=1n RISE=1 TARG id VAL=10n RISE=1
* -40 C
option temp=-40
dc VGS 0 0.6 0.002
let id = -i(VDS)
meas dc ioff_m40 FIND id AT=0
meas dc s_m40 TRIG id VAL=1n RISE=1 TARG id VAL=10n RISE=1
* back to 27 C with a small drain voltage
option temp=27
alter VDS dc=0.1
dc VGS 0 0.6 0.002
let id = -i(VDS)
meas dc ioff_vds01 FIND id AT=0
.endc
.end

See the Fix

* off current and subthreshold swing of an NMOS (W = 2, L = 0.15)
.lib sky130 tt
* lower gmin from its 1e-12 S default so that it does not add to the leakage
.options gmin=1e-18
XM1 d g 0 0 sky130_fd_pr__nfet_01v8 W=2 L=0.15
VDS d 0 1.8
VGS g 0 0
.control
* 27 C, VDS = 1.8 V
dc VGS 0 0.6 0.002
let id = -i(VDS)
meas dc ioff_27 FIND id AT=0
meas dc s_27 TRIG id VAL=1n RISE=1 TARG id VAL=10n RISE=1
* 125 C
option temp=125
dc VGS 0 0.6 0.002
let id = -i(VDS)
meas dc ioff_125 FIND id AT=0
meas dc s_125 TRIG id VAL=1n RISE=1 TARG id VAL=10n RISE=1
* -40 C
option temp=-40
dc VGS 0 0.6 0.002
let id = -i(VDS)
meas dc ioff_m40 FIND id AT=0
meas dc s_m40 TRIG id VAL=1n RISE=1 TARG id VAL=10n RISE=1
* back to 27 C with a small drain voltage
option temp=27
alter VDS dc=0.1
dc VGS 0 0.6 0.002
let id = -i(VDS)
meas dc ioff_vds01 FIND id AT=0
.endc
.end

Prints: ioff_27 = 1.019962e-12 ioff_m40 = 1.283695e-14

Half-Truth

"Leakage only depends on the threshold voltage."

It also rises steeply with temperature, here from 0.0128 pA at -40 °C to 152.7 pA at 125 °C, and with drain voltage through barrier lowering.

Source ASIC Point lesson E2.6 (measured)

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Subthreshold Swing and Leakage

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